Ryujinx/ChocolArm64
gdkchan 0b52ee6627
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
* Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements

* Remove useless space

* Address PR feedback

* Revert EmitVectorZero32_128 changes
2018-09-26 23:30:21 -03:00
..
Decoder
Decoder32
Events
Exceptions
Instruction Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405) 2018-09-26 23:30:21 -03:00
Instruction32
Memory Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405) 2018-09-26 23:30:21 -03:00
State
Translation
ABitUtils.cs
AOpCodeTable.cs
AOptimizations.cs
AThread.cs
ATranslatedSub.cs
ATranslatedSubType.cs
ATranslator.cs
ATranslatorCache.cs
ChocolArm64.csproj