2010-06-02 20:00:22 +02:00
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incdir "tests"
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include "dsp_base.inc"
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; We'll let dsp_base.inc catch exceptions
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;nop
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;nop
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;nop
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;nop
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;nop
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;nop
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;nop
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;nop
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;nop
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;nop
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;nop
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;nop
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;nop
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;halt
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;rti
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;halt
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sbset #0x06
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sbclr #0x03
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sbclr #0x04
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sbset #0x05
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lri $CR, #0x00ff
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lri $WR0, #0xffff
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lri $WR1, #0xffff
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lri $WR2, #0xffff
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lri $WR3, #0xffff
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set40
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m0
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clr15
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;step 1: context setup
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2020-06-02 02:50:02 +02:00
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call send_back
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2010-06-02 20:00:22 +02:00
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2015-01-11 06:17:29 +01:00
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call 0x807e ; loop until DSP->CPU mailbox is empty
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2010-06-02 20:00:22 +02:00
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si @DMBH, #0xdcd1
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si @DMBL, #0x0000 ; sendmail 0xdcd10000
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si @DIRQ, #0x0001
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2015-01-11 06:17:29 +01:00
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; wait for CPU mail == 0xabbaxxxx
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2010-06-02 20:00:22 +02:00
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wait_cpu_init:
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call 0x8078
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lrs $AC0.L, @CMBL
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cmpi $AC0.M, #0xabba
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jnz wait_cpu_init
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; Next mail has the mram addr of the data to fetch
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set16
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call 0x8078
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lrs $AX0.L, @CMBL
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andi $AC0.M, #0x0fff
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mrr $AX0.H, $AC0.M
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2015-01-13 04:28:12 +01:00
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lri $AX1.H, #0x0000 ; DSP-DRAM addr
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2010-06-02 20:00:22 +02:00
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lri $AX1.L, #0x0020 ; length (32 bytes = 16 words, word 9 and 10 are addr where result should DMA'd to in main mem)
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lri $IX3, #0x0000 ; there will be no ucode/iram upload
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2015-01-13 04:28:12 +01:00
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lri $AR0, #do_main ; return addr after DRAM upload
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2010-06-02 20:00:22 +02:00
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jmp 0x80bc ; DRAM upload !!
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; $AX0.H-$AX0.L - CPU(PPC) addr = mail & 0x0fffffff
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2015-01-13 04:28:12 +01:00
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; upload data from mainmem to DSP DRAM and jump to 0x41 after that
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2010-06-02 20:00:22 +02:00
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; ucode addr 0x0041
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do_main:
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2015-01-11 06:17:29 +01:00
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;step 2: got data from CPU, before going into BigCrazyFunction
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2010-06-02 20:00:22 +02:00
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call send_back
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call BigCrazyFunction ; <<------------- main crap is here!!!!!!!!!
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2015-01-11 06:17:29 +01:00
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call 0x807e ; loop until DSP->CPU mailbox is empty
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2010-06-02 20:00:22 +02:00
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si @DMBH, #0xdcd1
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si @DMBL, #0x0003 ; sendmail 0xdcd10003 (aka... calc is over, result is in main mem now)
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si @DIRQ, #0x0001
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set40
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2015-01-11 06:17:29 +01:00
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; wait for CPU to tell us what to do after calc'ing
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2010-06-02 20:00:22 +02:00
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wait_cpu_end:
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call 0x8078
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cmpi $AC0.M, #0xcdd1
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jnz wait_cpu_end
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lrs $AC0.M, @CMBL
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cmpi $AC0.M, #0x0001
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2015-01-11 06:17:29 +01:00
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jz PrepareBootUcode ; if CPU->DSP mail was 0xcdd10001 -> 005e_PrepareBootUcode()
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2010-06-02 20:00:22 +02:00
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cmpi $AC0.M, #0x0002
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2015-01-11 06:17:29 +01:00
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jz 0x8000 ; if CPU->DSP mail was 0xcdd10002 -> DSP reset ( jmp to irom(0x8000))
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2010-06-02 20:00:22 +02:00
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; THIS IS CUSTOM CODE
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cmpi $AC0.M, #0xbabe
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2015-01-11 06:17:29 +01:00
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jz end_of_test ; wait for DSP to be reset by CPU
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2010-06-02 20:00:22 +02:00
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2015-01-11 06:17:29 +01:00
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jmp wait_cpu_end ; wait for next mail from CPU
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2010-06-02 20:00:22 +02:00
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halt
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PrepareBootUcode:
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set16
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call 0x8078
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lrs $AC0.L, @CMBL
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call 0x8078
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lrs $AC0.L, @CMBL
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call 0x8078
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lrs $AC0.L, @CMBL
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call 0x8078
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lr $IX1, @CMBL
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andi $AC0.M, #0x0fff
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mrr $IX0, $AC0.M
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call 0x8078
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lr $IX3, @CMBL
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call 0x8078
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lr $IX2, @CMBL
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call 0x8078
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lr $AR0, @CMBL
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call 0x8078
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lrs $AX0.L, @CMBL
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andi $AC0.M, #0x0fff
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mrr $AX0.H, $AC0.M
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call 0x8078
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lrs $AX1.L, @CMBL
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call 0x8078
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lrs $AX1.H, @CMBL
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sbclr #0x05
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sbclr #0x06
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jmp 0x80b5 ; BootUcode()
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halt
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2015-01-13 04:28:12 +01:00
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; does some crazy stuff with data at DRAM @0x3/0x5/0x6/0x7 with help of some values from drom :)
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2010-06-02 20:00:22 +02:00
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; result is @0x22,@0x23 and written back to main memory to dmem-0x08:dmem-0x09
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BigCrazyFunction:
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; {
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clr $ACC0
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lri $AR1, #0x0010
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loopi #0x20
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srri @$AR1, $AC0.M
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call send_back ;3
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lr $AC1.M, @0x1456
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call send_back
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andi $AC1.M, #0xffd0
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call send_back
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clrp'mv : $AX1.L, $AC1.M ; assembler doesn't like .m here
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call send_back
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lri $AR0, #0x0000
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call send_back
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lri $IX2, #0x0000
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call send_back
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lri $AR2, #0x001f
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call send_back
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lr $AC0.M, @0x15f6
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call send_back
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lsl $ACC0, #8
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call send_back
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lr $AC1.M, @0x1766
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call send_back
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andi $AC1.M, #0x00ff
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call send_back
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mrr $AX0.H, $AC1.M
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call send_back
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call 0x88e5
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call send_back
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mrr $AX0.L, $AC0.L
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call send_back
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clr'mv $ACC0 : $AX1.H, $AC0.M ; assembler doesn't like .m here
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call send_back
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lrri $AC0.M, @$AR0
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call send_back
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lsr $ACC0, #-8
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call send_back
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mrr $AC1.M, $AC0.L
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call send_back
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mrr $AX0.H, $AC0.M
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call send_back
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call 0x8809
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call send_back
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call 0x8723
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call send_back
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dar $AR2
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call send_back
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clr'dr $ACC0 : $AR2
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call send_back
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lr $AC0.M, @0x166c
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call send_back
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lsl $ACC0, #4
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call send_back
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andi $AC0.M, #0xff00
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call send_back
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lr $AC1.M, @0x1231
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call send_back
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lsr $ACC1, #-8
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call send_back
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andi $AC1.M, #0x00ff
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call send_back
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mrr $AX0.H, $AC1.M
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call send_back
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call 0x88e5
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call send_back
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mrr $AX0.L, $AC0.L
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call send_back
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clr'mv $ACC0 : $AX1.H, $AC0.M ; assembler doesn't like .m here
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call send_back
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lrri $AC0.M, @$AR0
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call send_back
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lsr $ACC0, #-8
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call send_back
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mrr $AC1.M, $AC0.L
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call send_back
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mrr $AX0.H, $AC0.M
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call send_back
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call 0x8809
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call send_back
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call 0x8723
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call send_back
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clr $ACC0
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call send_back
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clr $ACC1
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call send_back
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lr $AC1.H, @0x0005
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call send_back
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asr16 $ACC1
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call send_back
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cmp
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call send_back ;46
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jz Unk_00e5
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call send_back ;47
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jl Unk_00f3
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call send_back ;48
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; if ( > ) {
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; length 12
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lri $AR2, #0x0010
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call send_back
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lri $IX2, #0x0001
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call send_back
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lr $AC0.H, @0x171b
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call send_back
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asr16 $ACC0
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call send_back
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neg $ACC1
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call send_back
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add $ACC1, $ACC0
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call send_back
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lsl $ACC1, #1
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call send_back
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mrr $AX0.H, $AC1.M
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call send_back
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lr $AC1.M, @0x0003
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call send_back
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lsl $ACC1, #4
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call send_back
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call 0x8809
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call send_back
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jmp Unk_0102
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call send_back ;60
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; } else if ( == 0) {
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; length 8
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Unk_00e5:
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lri $AR2, #0x0011
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call send_back
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lr $AC1.M, @0x0003
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call send_back
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lsl $ACC1, #1
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call send_back
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mrr $AX0.H, $AC1.M
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call send_back
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lr $AC0.M, @0x1043
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call send_back
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andi $AC0.M, #0xfff0
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call send_back
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call 0x88e5
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call send_back ;53
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jmp Unk_0102
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; } else if ( < ) {
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; length 10
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Unk_00f3:
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lri $AR2, #0x0010
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call send_back
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lri $IX2, #0x0001
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call send_back
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lr $AC0.H, @0x1285
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call send_back
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asr16 $ACC0
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call send_back
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add $ACC1, $ACC0
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call send_back
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lsl $ACC1, #1
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call send_back
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lr $AC0.M, @0x0003
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call send_back
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lsl $ACC0, #4
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call send_back
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mrr $AX0.H, $AC0.M
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call send_back
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call 0x8809
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call send_back ;57
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; }
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Unk_0102:
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lri $AR3, #0x0013
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call send_back ; either step 60, 53, 57
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srri @$AR3, $AC0.M
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call send_back
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clr's $ACC1 : @$AR3, $AC0.L
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call send_back
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lri $AR3, #0x0013
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call send_back
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lr $AC1.M, @0x0007
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call send_back
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lr $AC0.M, @0x11b8
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call send_back
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andi $AC0.M, #0xfff0 ;66
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call send_back
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mrr $AX0.H, $AC0.M
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call send_back
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;call 0x81f4
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mulxac'mv $AX0.H, $AX1.L, $ACC1 : $AX1.H, $AC0.M
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|
|
call send_back
|
|
|
|
|
asr16'ir $ACC1 : $AR1
|
|
|
|
|
call send_back ;66
|
|
|
|
|
srri @$AR3, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
clr's $ACC0 : @$AR3, $AC1.L
|
|
|
|
|
|
|
|
|
|
call send_back
|
|
|
|
|
lsl16 $ACC1
|
|
|
|
|
call send_back
|
|
|
|
|
|
|
|
|
|
;call 0x8458 ;66
|
|
|
|
|
mulxac'mv $AX0.H, $AX1.L, $ACC1 : $AX1.H, $AC0.M
|
|
|
|
|
call send_back
|
|
|
|
|
asr16 $ACC1
|
|
|
|
|
call send_back
|
|
|
|
|
srri @$AR3, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
clr's $ACC0 : @$AR3, $AC1.L
|
|
|
|
|
call send_back
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
call send_back
|
|
|
|
|
set40
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
lri $AR2, #0x0015
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
lr $AC0.M, @0x0006
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
lr $AX0.H, @0x165b
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
call 0x88e5
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
asr $ACC0, #-3
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
lsl $ACC0, #3
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
srri @$AR2, $AC0.M
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
srri @$AR2, $AC0.L
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
lri $AR2, #0x0016
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
lr $AC0.M, @0x1723
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
asr $ACC0, #-12
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
lr $AX0.H, @0x166b
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
call 0x88e5
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
tst $ACC0
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
jge Unk_012e
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
|
|
|
|
|
clr $ACC0
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
|
|
|
|
|
Unk_012e:
|
|
|
|
|
asr $ACC0, #-3
|
2020-06-02 02:50:02 +02:00
|
|
|
call send_back
|
2010-06-02 20:00:22 +02:00
|
|
|
set16
|
|
|
|
|
;step 4
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC1.M, @0x1491
|
|
|
|
|
call send_back
|
|
|
|
|
andi $AC1.M, #0xd0f0
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $IX1, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC1.M, @0x1468
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC1.H, @0x11fc
|
|
|
|
|
call send_back
|
|
|
|
|
lsr $ACC1, #-4
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $IX2, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC1.H, @0x11b8
|
|
|
|
|
call send_back
|
|
|
|
|
asr16 $ACC1
|
|
|
|
|
call send_back
|
|
|
|
|
lsl $ACC0, #24
|
|
|
|
|
call send_back
|
|
|
|
|
lsr $ACC0, #-8
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $AX0.H, $AC0.M
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $AC1.M, $AC0.M
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $AX1.H, $IX1
|
|
|
|
|
call send_back
|
|
|
|
|
andr $AC0.M, $AX1.H
|
|
|
|
|
call send_back
|
|
|
|
|
lsl $ACC0, #2
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $AX1.H, $IX2
|
|
|
|
|
call send_back
|
|
|
|
|
andr $AC1.M, $AX1.H
|
|
|
|
|
call send_back
|
|
|
|
|
lsl $ACC1, #1
|
|
|
|
|
call send_back
|
|
|
|
|
add $ACC0, $ACC1
|
|
|
|
|
call send_back
|
|
|
|
|
lsl $ACC1, #24
|
|
|
|
|
call send_back
|
|
|
|
|
asr16 $ACC1
|
|
|
|
|
call send_back
|
|
|
|
|
andr $AC1.M, $AX0.H
|
|
|
|
|
call send_back
|
|
|
|
|
add $ACC0, $ACC1
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC1.M, @0x0012
|
|
|
|
|
call send_back
|
|
|
|
|
orc $AC1.M, $AC0.M
|
|
|
|
|
call send_back
|
|
|
|
|
sr @0x0012, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
lsr $ACC0, #-16
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC1.M, @0x0011
|
|
|
|
|
call send_back
|
|
|
|
|
orc $AC1.M, $AC0.M
|
|
|
|
|
call send_back
|
|
|
|
|
sr @0x0011, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $AC1.L, $IX1
|
|
|
|
|
call send_back
|
|
|
|
|
lsl $ACC1, #1
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $AC1.M, $IX2
|
|
|
|
|
call send_back
|
|
|
|
|
lsl16 $ACC1
|
|
|
|
|
call send_back
|
|
|
|
|
asr $ACC1, #-8
|
|
|
|
|
call send_back
|
|
|
|
|
lsr16 $ACC1
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $AX0.H, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $AX1.H, $AC1.L
|
|
|
|
|
call send_back
|
|
|
|
|
clr $ACC0
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC0.M, @0x0011
|
|
|
|
|
call send_back
|
|
|
|
|
andr $AC0.M, $AX0.H
|
|
|
|
|
call send_back
|
|
|
|
|
clr $ACC1
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC1.M, @0x0012
|
|
|
|
|
call send_back
|
|
|
|
|
andr $AC1.M, $AX0.H
|
|
|
|
|
call send_back
|
|
|
|
|
add $ACC0, $ACC1
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC1.M, @0x0012
|
|
|
|
|
call send_back
|
|
|
|
|
lsr $ACC1, #-8
|
|
|
|
|
call send_back
|
|
|
|
|
add $ACC0, $ACC1
|
|
|
|
|
call send_back
|
|
|
|
|
|
|
|
|
|
call send_back
|
|
|
|
|
clr $ACC1
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $AC1.M, $AC0.M
|
|
|
|
|
call send_back
|
|
|
|
|
lsl $ACC1, #8
|
|
|
|
|
call send_back
|
|
|
|
|
orr $AC1.M, $AX1.H
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC0.M, @0x0011
|
|
|
|
|
call send_back
|
|
|
|
|
orc $AC0.M, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC1.M, @0x0012
|
|
|
|
|
call send_back
|
|
|
|
|
orr $AC1.M, $AX1.H
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $IX1, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AX0.H, @0x15f1
|
|
|
|
|
call send_back
|
|
|
|
|
andr $AC1.M, $AX0.H
|
|
|
|
|
call send_back
|
|
|
|
|
jz else_0192
|
|
|
|
|
call send_back
|
|
|
|
|
; if () {
|
|
|
|
|
|
|
|
|
|
lr $AC1.M, @0x10e2
|
|
|
|
|
call send_back
|
|
|
|
|
lsl $ACC1, #8
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $AX0.H, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC1.M, @0x103b
|
|
|
|
|
call send_back
|
|
|
|
|
decm $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
orr $AC1.M, $AX0.H
|
|
|
|
|
call send_back
|
|
|
|
|
xorc $AC0.M, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
sr @0x0022, $AC0.M
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC0.L, @0x1229
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC1.L, @0x11f8
|
|
|
|
|
call send_back
|
|
|
|
|
sub $ACC0, $ACC1
|
|
|
|
|
call send_back
|
|
|
|
|
lsl16 $ACC0
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $AC1.M, $IX1
|
|
|
|
|
call send_back
|
|
|
|
|
xorc $AC0.M, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
jmp Unk_01a5
|
|
|
|
|
call send_back
|
|
|
|
|
|
|
|
|
|
; } else {
|
|
|
|
|
else_0192:
|
|
|
|
|
lr $AC1.M, @0x10ca
|
|
|
|
|
call send_back
|
|
|
|
|
lsl $ACC1, #8
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $AX0.H, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC1.M, @0x1043
|
|
|
|
|
call send_back
|
|
|
|
|
incm $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
orr $AC1.M, $AX0.H
|
|
|
|
|
call send_back
|
|
|
|
|
xorc $AC0.M, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
sr @0x0022, $AC0.M
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC0.L, @0x1259
|
|
|
|
|
call send_back
|
|
|
|
|
lr $AC1.L, @0x16fe
|
|
|
|
|
call send_back
|
|
|
|
|
add $ACC0, $ACC1
|
|
|
|
|
call send_back
|
|
|
|
|
lsl16 $ACC0
|
|
|
|
|
call send_back
|
|
|
|
|
mrr $AC1.M, $IX1
|
|
|
|
|
call send_back
|
|
|
|
|
xorc $AC0.M, $AC1.M
|
|
|
|
|
call send_back
|
|
|
|
|
; }
|
|
|
|
|
|
|
|
|
|
Unk_01a5:
|
|
|
|
|
; this is where result is written to main memory
|
2015-01-11 06:17:29 +01:00
|
|
|
; DSP mem 0x20-0x23 (8 bytes) are written back (DMA limitation),
|
2010-06-02 20:00:22 +02:00
|
|
|
; but only values @22 and @23 were modified (result is 32bit)
|
|
|
|
|
sr @0x0023, $AC0.M
|
|
|
|
|
call send_back
|
2015-01-11 06:17:29 +01:00
|
|
|
lr $AX0.H, @0x0008 ; CPU addr high
|
2010-06-02 20:00:22 +02:00
|
|
|
call send_back
|
2015-01-11 06:17:29 +01:00
|
|
|
lr $AX0.L, @0x0009 ; CPU addr low
|
2010-06-02 20:00:22 +02:00
|
|
|
call send_back
|
2015-01-11 06:17:29 +01:00
|
|
|
lri $AX1.H, #0x0020 ; DSP addr
|
2010-06-02 20:00:22 +02:00
|
|
|
call send_back
|
|
|
|
|
lri $AX1.L, #0x0008 ; length
|
|
|
|
|
call send_back
|
2015-01-13 04:28:12 +01:00
|
|
|
lri $IX3, #0x0000 ; there will be no iram DMA
|
2010-06-02 20:00:22 +02:00
|
|
|
call send_back
|
2015-01-13 04:28:12 +01:00
|
|
|
call 0x808b ; DRAM->CPU <<<--- important!!
|
2010-06-02 20:00:22 +02:00
|
|
|
call send_back
|
|
|
|
|
ret
|
|
|
|
|
; }
|
|
|
|
|
|
|
|
|
|
; Free some space for the TROJAN CODEZ
|
|
|
|
|
;nop
|
|
|
|
|
;nop
|
|
|
|
|
;nop
|
|
|
|
|
;nop
|
|
|
|
|
;nop
|
|
|
|
|
;nop
|
|
|
|
|
;nop
|
|
|
|
|
;nop
|
|
|
|
|
;nop
|
|
|
|
|
;nop
|
|
|
|
|
;nop
|
|
|
|
|
;nop
|
