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65 lines
1.2 KiB
Plaintext
65 lines
1.2 KiB
Plaintext
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incdir "tests"
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include "dsp_base.inc"
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; Test parameters
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lri $AC0.M, #0x0000 ; start
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lri $AC0.L, #0x0000 ; start
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lri $AC1.M, #0x0000 ; end
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lri $AC1.L, #0x0011 ; end
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; Reset some registers
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lri $AC0.H, #0xffff
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sr @0xffda, $AC0.H ; pred scale
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sr @0xffdb, $AC0.H ; yn1
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sr @0xffdc, $AC0.H ; yn2
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; Set the sample format
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lri $AC0.H, #0x0
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sr @0xffd1, $AC0.H
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; Set the starting and current address
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srs @ACSAH, $AC0.M
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srs @ACCAH, $AC0.M
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srs @ACSAL, $AC0.L
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srs @ACCAL, $AC0.L
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; Set the ending address
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srs @ACEAH, $AC1.M
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srs @ACEAL, $AC1.L
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call load_hw_reg_to_regs
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call send_back ; check the accelerator regs before a read
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bloopi #40, end_of_loop
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lr $IX3, @ARAM
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call load_hw_reg_to_regs
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call send_back ; after a read
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end_of_loop:
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nop
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jmp end_of_test
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load_hw_reg_to_regs:
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lr $AR0, @0xffd1 ; format
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lr $AR1, @0xffd2 ; unknown
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lr $AR2, @0xffda ; pred scale
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lr $AR3, @0xffdb ; yn1
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lr $IX0, @0xffdc ; yn2
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lr $IX1, @0xffdf ; unknown accelerator register
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lri $AC0.H, #0
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lrs $AC0.M, @ACSAH
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lrs $AC0.L, @ACSAL
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lri $AC1.H, #0
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lrs $AC1.M, @ACEAH
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lrs $AC1.L, @ACEAL
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lrs $AX0.H, @ACCAH
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lrs $AX0.L, @ACCAL
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lrs $AX1.H, @ACCAH
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lrs $AX1.L, @ACCAL
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lrs $AX1.H, @ACCAH
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lrs $AX1.L, @ACCAL
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ret
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