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018c85c248
Commit Graph

48 Commits

Author SHA1 Message Date
Lioncash
018c85c248 Arm64Emitter: Mark trivial functions as constexpr 2015-10-22 15:22:38 -04:00
Lioncash
19ac565e0d Common: Move asserts to their own header 2015-09-26 18:51:27 -04:00
Ryan Houdek
2ad26ab3e9 [AArch64] Fix Test&Branch to relative location instructions. 
Wasn't masking by the size of the offset encoding so negative values were killing the instruction
Missed commiting this in my integer gatherpipe PR.
Fixes crashing on AArch64.
 2015-09-07 13:38:58 -05:00
Ryan Houdek
d003934b8a Merge pull request #2929 from Sonicadvance1/aarch64_optimize_gpr_flush 
Aarch64 optimize gpr flush
 2015-08-31 10:55:45 -05:00
Ryan Houdek
f2c17436ab [AArch64] Fix issue in emitter. 
Loadstore pairs support only signed offsets, not unsigned.
 2015-08-30 23:05:59 -05:00
Ryan Houdek
b907576510 [AArch64] Support profiling by cycle counters if they are available to EL0 2015-08-30 10:25:16 -05:00
Ryan Houdek
4fa23abbe1 [AArch64] Implement MOVI and ORR(imm) in the NEON emitter. 2015-08-23 15:34:53 -05:00
degasus
9bfff0d461 JitArm64: Fix jit clearing 
We have to reset m_lastCacheFlushEnd on clearing.
 2015-08-15 11:41:01 +02:00
Lioncash
144ea9f4aa Arm64Emitter: Fix encoding of '2-reg misc' variant of FCMEQ 2015-08-10 19:48:36 -04:00
Ryan Houdek
922d476dab [AArch64] Fix FCMGE instruction encoding. 
Fixes a crash when ps_sel is used (PSO 1&2 intro movies).
 2015-08-09 14:54:55 -05:00
degasus
b8dd68beef JitArm64: Far Code Cache 2015-07-12 09:41:32 +02:00
Lioncash
d09d59007a Arm64Emitter: Add a missing const specifier for an array table 2015-07-02 11:09:44 -04:00
Ryan Houdek
afc3d30f5c [AArch64] Implement BFI & UBFIZ in the emitter. 
Also fixes a bug in the UBFX instruction emitter. Naughty Naughty PPSSPP, not testing emitter functions you add.
 2015-06-29 19:00:22 -05:00
Ryan Houdek
5dc148159f [AArch64] Implement {U, S}QXTN{,2} 
Also split out XTN to XTN and XTN2.
 2015-06-13 23:16:17 -05:00
Lioncash
74b359e390 Arm64Emitter: Remove unused variable from EncodeLoadStoreRegisterOffset 2015-06-13 14:27:15 -04:00
Ryan Houdek
3d2b116323 [AArch64] Implement a couple instructions in the emitter. 
Implements LD2R.
Implements LD1R/LD2R with post-indexing support.
Implements vector min/max instructions.
 2015-06-09 18:10:56 -05:00
Ryan Houdek
8ae12d8005 [AArch64] Add ASIMD LDR/STR with register offset 2015-06-07 19:53:05 -05:00
Ryan Houdek
05b72c5d31 [AArch64] Upstream PPSSPP's emitter changes. 
Requires a minor change to in the JIT to make sure everything still works.
 2015-06-07 19:50:21 -05:00
Tillmann Karras
30ebb2459e Set copyright year to when a file was created 2015-05-25 13:22:31 +02:00
Tillmann Karras
cefcb0ace9 Update license headers to GPLv2+ 2015-05-25 13:22:31 +02:00
Ryan Houdek
f6511c3ba5 [AArch64] Add an assert to SMOV in the emitter. 
SMOV doesn't have an encoding for moving a 32bit element to a 32bit GPR.
One should use UMOV if they want that.
 2015-03-08 12:29:45 -05:00
Ryan Houdek
fbdee7b15f [AArch64] Handle FPR island registers in a less dumb way. 2015-03-03 00:30:05 -06:00
Ryan Houdek
f1a9db9bdc [AArch64] Stop violating the AAPCS64 so much. 2015-03-02 11:21:15 -06:00
Ryan Houdek
fad46729b0 [AArch64] Implemented paired pushing/popping for the VFP. 
A bit more efficient if we are only pushing two VFP registers.
We can probably be a bit more efficient in the future by mixing paired loadstores in to the other paths as well.
 2015-03-02 06:27:47 -06:00
Ryan Houdek
39e357d62d [AArch64] Implement VFP loadstore paired in the emitter. 2015-03-02 06:27:17 -06:00
Ryan Houdek
8b8310d28c [AArch64] Optimize FPR pushing and popping. 
Previously on FPR pushing and popping we would do a single STR/LDR per quad FPR we wanted to push/pop.
In most of our cases when we are pushing and popping VFP registers they will be consecutive registers that will save more efficiently using the NEON
loadstores that can do up to four quad registers.
So this can potentially cutting instructions down to ~1/4th the amount of instructions if the registers are all consecutive.

On the Cortex-A57 this is basically just an icache improvement, but on the Nvidia Denver this may be optimized to be more efficient. Either way it's a
win.
 2015-03-02 06:27:13 -06:00
Ryan Houdek
120df4c688 [AArch64] Implement loadstore unscaled. 2015-02-16 22:00:43 -06:00
Ryan Houdek
814aaaf538 [AArch64] Implement a couple of emitter instructions. 
These will be used with the vertex loader JIT recompiler.
 2015-02-13 12:16:06 -06:00
Ryan Houdek
20dae1f210 [AArch64] Fix a bunch of emitter asserts. 
Since I've added the msg handler. I found all these asserts that were backwards. So they were asserting on the correct arguments.
 2015-02-13 12:16:05 -06:00
Ryan Houdek
c340a324bc Merge pull request #1947 from Sonicadvance1/AArch64_tu_tl_merge 
[AArch64] Implement TU/TL merging.
 2015-01-25 23:07:32 -06:00
Ryan Houdek
f24c466e7e [AArch64] Fix AArch64 instruction encoding. 2015-01-25 17:26:18 -06:00
Ryan Houdek
6470227a39 [AArch64] Minor fix in the UMULH/SMULH. 
These two instructions ignore the register encoded in to RA.
 2015-01-22 18:08:49 -06:00
Ryan Houdek
217c2c9d6a [AArch64] Add some more scalar VFP ops to the emitter. 2015-01-20 16:34:32 -06:00
Ryan Houdek
8d5947efac [AArch64] Emitter improvements. 
Adds a bunch of new instructions to the emitter.
 2015-01-18 16:25:40 -06:00
Ryan Houdek
c511ee763a [AArch64] Add the float emitter. 2015-01-08 19:55:31 -06:00
Ryan Houdek
5a0133c478 [AArch64] Add a few more VFP register helpers. 
Renames Is128Bit to IsQuad to line up more with the other helpers.
 2015-01-07 13:05:55 -06:00
Ryan Houdek
0a23ca9461 [AArch64] Add MUL/MNEG instruction aliases to the emitter. 2015-01-07 13:03:01 -06:00
Ryan Houdek
d2eaba5cb7 [AArch64] Minor MOVI2R improvement. 
Use the ZR for both input arguments in the case the immediate is the maximum immediate value.
This allows it to be aliased to MVN when disassembling.
 2015-01-07 13:00:39 -06:00
Ryan Houdek
8dba84dd7c [AArch64] Fix 8 & 16 bit loadstore indexes. 
I wasn't bit shifting correctly for 8 and 16bit loadstores.
 2015-01-07 12:58:37 -06:00
Ryan Houdek
f4f59ea71e [AArch64] Fix ADDS/SUBS emitter functions. 
These weren't emitting the flag bit. So they were regular ADD and SUB emitters.
 2015-01-07 12:56:45 -06:00
Ryan Houdek
d3c2e8fb0a [AArch64] Improvements to the AArch64 emitter. 
Fixes issues with negative offsets in loadstore instructions.
Adds ADRP/ADR instructions.
Optimizes MOVI2R function to take advantage of ADRP on pointers, can change a 3 instruction operation down to one.
Adds GPR push/pop operations for ABI related things.
 2014-12-20 19:35:52 -06:00
Ryan Houdek
2c39d4044d [AArch64] Add loadstore paired emitter instructions. 2014-12-02 21:08:34 -06:00
Lioncash
e9b09a4c9f Arm(64)Emitter: Make some variables static 2014-11-25 23:27:48 -05:00
Ryan Houdek
7608e3f11e Add AArch64 emitter aliases for MOV and MVN. 2014-09-18 16:30:40 -05:00
Ryan Houdek
17d31ecd6c Fix AArch64 MOVI2R helper function. 
In the case of a zero immediate, it wouldn't generate code at all.
Also in the case of max u32/u64, use ORN to optimize it.
 2014-09-12 05:45:10 -05:00
Ryan Houdek
24f6c98a55 Add sign extending aliases to the ARM64Emitter. 2014-09-10 17:52:54 -05:00
Lioncash
bc331ee809 Common: Fix code styling in Arm64Emitter 2014-09-08 23:39:20 -04:00
Ryan Houdek
f107b5e176 [AArch64-emitter] Initial work on a emitter for 64bit ARM. 
I've tested a few instruction encodings and am expecting most to work as long as one stays away from VFP/SIMD.
This implements mostly instructions to bring up an initial JIT with integer support.
This can be improved to allow ease of use functions in the future, dealing with the raw imms/immr encodings is probably the worst thing ever.
 2014-09-06 20:13:44 -05:00