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Hardware testing indicated that SRS uses a different list of registers than LRS (specifically, acS.h can be used with SRSH but not LRS, and SRS does not support AX registers, and there are 2 encodings that do nothing).
132 lines
2.6 KiB
Plaintext
132 lines
2.6 KiB
Plaintext
incdir "tests"
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include "dsp_base.inc"
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test_main:
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; Test registers used by LRS and SRS
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LRI $CR, #0x0000
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CALL clear_regs
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CALL store_mem_sr
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; Write with SR, read with LR
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LRI $AR0, #0xA00A
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CALL create_pattern
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CALL store_mem_sr
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CALL send_back
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CALL clear_regs
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CALL read_mem_lr
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CALL send_back
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; Write with SR, read with LRS
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LRI $AR0, #0xB00B
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CALL create_pattern
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CALL store_mem_sr
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CALL send_back
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CALL clear_regs
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CALL read_mem_lrs
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CALL send_back
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; Write with SRS, read with LR
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LRI $AR0, #0xC00C
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CALL create_pattern
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CALL store_mem_srs
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CALL send_back
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CALL clear_regs
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CALL read_mem_lr
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CALL send_back
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; Write with SR, read with LRS
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LRI $AR0, #0xD00D
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CALL create_pattern
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CALL store_mem_srs
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CALL send_back
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CALL clear_regs
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CALL read_mem_lrs
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CALL send_back
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; We're done, DO NOT DELETE THIS LINE
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JMP end_of_test
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create_pattern:
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LRI $IX0, #0x0110
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MRR $AX0.L, $AR0
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ADDARN $AR0, $IX0
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MRR $AX1.L, $AR0
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ADDARN $AR0, $IX0
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MRR $AX0.H, $AR0
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ADDARN $AR0, $IX0
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MRR $AX1.H, $AR0
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ADDARN $AR0, $IX0
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MRR $AC0.L, $AR0
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ADDARN $AR0, $IX0
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MRR $AC1.L, $AR0
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ADDARN $AR0, $IX0
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MRR $AC0.M, $AR0
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ADDARN $AR0, $IX0
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MRR $AC1.M, $AR0
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ADDARN $AR0, $IX0
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; AC0.H and AC1.H have odd results since they're 8-bit sign-extended, but that's fine.
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MRR $AC0.H, $AR0
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ADDARN $AR0, $IX0
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MRR $AC1.H, $AR0
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RET
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clear_regs:
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LRI $AX0.L, #0x0000
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LRI $AX1.L, #0x0000
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LRI $AX0.H, #0x0000
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LRI $AX1.H, #0x0000
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LRI $AC0.L, #0x0000
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LRI $AC1.L, #0x0000
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LRI $AC0.M, #0x0000
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LRI $AC1.M, #0x0000
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LRI $AC0.H, #0x0000
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LRI $AC1.H, #0x0000
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RET
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read_mem_lr:
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LR $AX0.L, @0x0000
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LR $AX1.L, @0x0001
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LR $AX0.H, @0x0002
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LR $AX1.H, @0x0003
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LR $AC0.L, @0x0004
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LR $AC1.L, @0x0005
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LR $AC0.M, @0x0006
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LR $AC1.M, @0x0007
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RET
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read_mem_lrs:
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LRS $AX0.L, @0x00
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LRS $AX1.L, @0x01
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LRS $AX0.H, @0x02
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LRS $AX1.H, @0x03
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LRS $AC0.L, @0x04
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LRS $AC1.L, @0x05
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LRS $AC0.M, @0x06
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LRS $AC1.M, @0x07
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RET
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store_mem_sr:
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SR @0x0000, $AX0.L
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SR @0x0001, $AX1.L
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SR @0x0002, $AX0.H
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SR @0x0003, $AX1.H
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SR @0x0004, $AC0.L
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SR @0x0005, $AC1.L
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SR @0x0006, $AC0.M
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SR @0x0007, $AC1.M
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RET
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store_mem_srs:
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; For future compatibility these have been changed to cw.
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; The way the instructions were originally encoded is commented,
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; but this does not match their behavior.
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cw 0x2800 ; SRS @0x00, $AX0.L - actually SRSH @0x00, $AC0.H
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cw 0x2901 ; SRS @0x01, $AX1.L - actually SRSH @0x01, $AC1.H
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cw 0x2A02 ; SRS @0x02, $AX0.H - actually unknown, no store performed
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cw 0x2B03 ; SRS @0x03, $AX1.H - actually unknown, no store performed
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cw 0x2C04 ; SRS @0x04, $AC0.L
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cw 0x2D05 ; SRS @0x05, $AC1.L
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cw 0x2E06 ; SRS @0x06, $AC0.M
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cw 0x2F07 ; SRS @0x07, $AC1.M
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RET
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