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shader/arithmetic_integer: Implement CC for IADD
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parent
ffc5ec6fa8
commit
255197e643
2
externals/sirit
vendored
2
externals/sirit
vendored
@ -1 +1 @@
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Subproject commit a712959f1e373a33b48042b5934e288a243d5954
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Subproject commit 414fc4dbd28d8fe48f735a0c389db8a234f733c0
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@ -1870,6 +1870,14 @@ private:
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return GenerateBinaryInfix(operation, ">=", Type::Bool, type, type);
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return GenerateBinaryInfix(operation, ">=", Type::Bool, type, type);
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}
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}
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Expression LogicalAddCarry(Operation operation) {
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const std::string carry = code.GenerateTemporary();
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code.AddLine("uint {};", carry);
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code.AddLine("uaddCarry({}, {}, {});", VisitOperand(operation, 0).AsUint(),
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VisitOperand(operation, 1).AsUint(), carry);
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return {fmt::format("({} != 0)", carry), Type::Bool};
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}
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Expression LogicalFIsNan(Operation operation) {
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Expression LogicalFIsNan(Operation operation) {
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return GenerateUnary(operation, "isnan", Type::Bool, Type::Float);
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return GenerateUnary(operation, "isnan", Type::Bool, Type::Float);
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}
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}
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@ -2441,6 +2449,8 @@ private:
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&GLSLDecompiler::LogicalNotEqual<Type::Uint>,
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&GLSLDecompiler::LogicalNotEqual<Type::Uint>,
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&GLSLDecompiler::LogicalGreaterEqual<Type::Uint>,
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&GLSLDecompiler::LogicalGreaterEqual<Type::Uint>,
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&GLSLDecompiler::LogicalAddCarry,
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&GLSLDecompiler::Logical2HLessThan<false>,
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&GLSLDecompiler::Logical2HLessThan<false>,
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&GLSLDecompiler::Logical2HEqual<false>,
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&GLSLDecompiler::Logical2HEqual<false>,
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&GLSLDecompiler::Logical2HLessEqual<false>,
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&GLSLDecompiler::Logical2HLessEqual<false>,
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@ -1584,6 +1584,15 @@ private:
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return {OpCompositeConstruct(t_half, low, high), Type::HalfFloat};
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return {OpCompositeConstruct(t_half, low, high), Type::HalfFloat};
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}
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}
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Expression LogicalAddCarry(Operation operation) {
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const Id op_a = AsUint(Visit(operation[0]));
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const Id op_b = AsUint(Visit(operation[1]));
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const Id result = OpIAddCarry(TypeStruct({t_uint, t_uint}), op_a, op_b);
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const Id carry = OpCompositeExtract(t_uint, result, 1);
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return {OpINotEqual(t_bool, carry, Constant(t_uint, 0)), Type::Bool};
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}
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Expression LogicalAssign(Operation operation) {
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Expression LogicalAssign(Operation operation) {
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const Node& dest = operation[0];
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const Node& dest = operation[0];
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const Node& src = operation[1];
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const Node& src = operation[1];
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@ -2518,6 +2527,8 @@ private:
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&SPIRVDecompiler::Binary<&Module::OpINotEqual, Type::Bool, Type::Uint>,
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&SPIRVDecompiler::Binary<&Module::OpINotEqual, Type::Bool, Type::Uint>,
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&SPIRVDecompiler::Binary<&Module::OpUGreaterThanEqual, Type::Bool, Type::Uint>,
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&SPIRVDecompiler::Binary<&Module::OpUGreaterThanEqual, Type::Bool, Type::Uint>,
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&SPIRVDecompiler::LogicalAddCarry,
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&SPIRVDecompiler::Binary<&Module::OpFOrdLessThan, Type::Bool2, Type::HalfFloat>,
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&SPIRVDecompiler::Binary<&Module::OpFOrdLessThan, Type::Bool2, Type::HalfFloat>,
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&SPIRVDecompiler::Binary<&Module::OpFOrdEqual, Type::Bool2, Type::HalfFloat>,
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&SPIRVDecompiler::Binary<&Module::OpFOrdEqual, Type::Bool2, Type::HalfFloat>,
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&SPIRVDecompiler::Binary<&Module::OpFOrdLessThanEqual, Type::Bool2, Type::HalfFloat>,
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&SPIRVDecompiler::Binary<&Module::OpFOrdLessThanEqual, Type::Bool2, Type::HalfFloat>,
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@ -40,10 +40,26 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) {
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op_a = GetOperandAbsNegInteger(op_a, false, instr.alu_integer.negate_a, true);
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op_a = GetOperandAbsNegInteger(op_a, false, instr.alu_integer.negate_a, true);
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op_b = GetOperandAbsNegInteger(op_b, false, instr.alu_integer.negate_b, true);
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op_b = GetOperandAbsNegInteger(op_b, false, instr.alu_integer.negate_b, true);
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const Node value = Operation(OperationCode::IAdd, PRECISE, op_a, op_b);
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Node value = Operation(OperationCode::IAdd, op_a, op_b);
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SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
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if (instr.generates_cc) {
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SetRegister(bb, instr.gpr0, value);
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const Node i0 = Immediate(0);
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Node zero = Operation(OperationCode::LogicalIEqual, value, i0);
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Node sign = Operation(OperationCode::LogicalILessThan, value, i0);
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Node carry = Operation(OperationCode::LogicalAddCarry, op_a, op_b);
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Node pos_a = Operation(OperationCode::LogicalIGreaterThan, op_a, i0);
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Node pos_b = Operation(OperationCode::LogicalIGreaterThan, op_b, i0);
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Node pos = Operation(OperationCode::LogicalAnd, std::move(pos_a), std::move(pos_b));
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Node overflow = Operation(OperationCode::LogicalAnd, pos, sign);
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SetInternalFlag(bb, InternalFlag::Zero, std::move(zero));
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SetInternalFlag(bb, InternalFlag::Sign, std::move(sign));
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SetInternalFlag(bb, InternalFlag::Carry, std::move(carry));
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SetInternalFlag(bb, InternalFlag::Overflow, std::move(overflow));
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}
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SetRegister(bb, instr.gpr0, std::move(value));
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break;
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break;
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}
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}
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case OpCode::Id::IADD3_C:
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case OpCode::Id::IADD3_C:
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@ -132,6 +132,8 @@ enum class OperationCode {
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LogicalUNotEqual, /// (uint a, uint b) -> bool
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LogicalUNotEqual, /// (uint a, uint b) -> bool
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LogicalUGreaterEqual, /// (uint a, uint b) -> bool
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LogicalUGreaterEqual, /// (uint a, uint b) -> bool
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LogicalAddCarry, /// (uint a, uint b) -> bool
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Logical2HLessThan, /// (MetaHalfArithmetic, f16vec2 a, f16vec2) -> bool2
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Logical2HLessThan, /// (MetaHalfArithmetic, f16vec2 a, f16vec2) -> bool2
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Logical2HEqual, /// (MetaHalfArithmetic, f16vec2 a, f16vec2) -> bool2
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Logical2HEqual, /// (MetaHalfArithmetic, f16vec2 a, f16vec2) -> bool2
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Logical2HLessEqual, /// (MetaHalfArithmetic, f16vec2 a, f16vec2) -> bool2
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Logical2HLessEqual, /// (MetaHalfArithmetic, f16vec2 a, f16vec2) -> bool2
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