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https://github.com/yuzu-mirror/yuzu.git
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shader_decode: SULD.D implement bits64 and reverse shader ir init method to removed shader stage.
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730f9b55b3
commit
2906372ba1
@ -234,7 +234,7 @@ Shader CachedShader::CreateStageFromMemory(const ShaderParameters& params,
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const std::size_t size_in_bytes = code.size() * sizeof(u64);
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const std::size_t size_in_bytes = code.size() * sizeof(u64);
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auto registry = std::make_shared<Registry>(shader_type, params.system.GPU().Maxwell3D());
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auto registry = std::make_shared<Registry>(shader_type, params.system.GPU().Maxwell3D());
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const ShaderIR ir(code, shader_type, STAGE_MAIN_OFFSET, COMPILER_SETTINGS, *registry);
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const ShaderIR ir(code, STAGE_MAIN_OFFSET, COMPILER_SETTINGS, *registry);
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// TODO(Rodrigo): Handle VertexA shaders
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// TODO(Rodrigo): Handle VertexA shaders
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// std::optional<ShaderIR> ir_b;
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// std::optional<ShaderIR> ir_b;
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// if (!code_b.empty()) {
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// if (!code_b.empty()) {
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@ -264,7 +264,7 @@ Shader CachedShader::CreateKernelFromMemory(const ShaderParameters& params, Prog
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auto& engine = params.system.GPU().KeplerCompute();
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auto& engine = params.system.GPU().KeplerCompute();
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auto registry = std::make_shared<Registry>(ShaderType::Compute, engine);
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auto registry = std::make_shared<Registry>(ShaderType::Compute, engine);
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const ShaderIR ir(code, ShaderType::Compute, KERNEL_MAIN_OFFSET, COMPILER_SETTINGS, *registry);
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const ShaderIR ir(code, KERNEL_MAIN_OFFSET, COMPILER_SETTINGS, *registry);
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const u64 uid = params.unique_identifier;
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const u64 uid = params.unique_identifier;
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auto program = BuildShader(params.device, ShaderType::Compute, uid, ir, *registry);
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auto program = BuildShader(params.device, ShaderType::Compute, uid, ir, *registry);
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@ -341,7 +341,7 @@ void ShaderCacheOpenGL::LoadDiskCache(const std::atomic_bool& stop_loading,
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const bool is_compute = entry.type == ShaderType::Compute;
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const bool is_compute = entry.type == ShaderType::Compute;
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const u32 main_offset = is_compute ? KERNEL_MAIN_OFFSET : STAGE_MAIN_OFFSET;
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const u32 main_offset = is_compute ? KERNEL_MAIN_OFFSET : STAGE_MAIN_OFFSET;
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auto registry = MakeRegistry(entry);
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auto registry = MakeRegistry(entry);
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const ShaderIR ir(entry.code, entry.type, main_offset, COMPILER_SETTINGS, *registry);
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const ShaderIR ir(entry.code, main_offset, COMPILER_SETTINGS, *registry);
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std::shared_ptr<OGLProgram> program;
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std::shared_ptr<OGLProgram> program;
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if (precompiled_entry) {
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if (precompiled_entry) {
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@ -162,7 +162,7 @@ CachedShader::CachedShader(Core::System& system, Tegra::Engines::ShaderType stag
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ProgramCode program_code, u32 main_offset)
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ProgramCode program_code, u32 main_offset)
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: RasterizerCacheObject{host_ptr}, gpu_addr{gpu_addr}, cpu_addr{cpu_addr},
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: RasterizerCacheObject{host_ptr}, gpu_addr{gpu_addr}, cpu_addr{cpu_addr},
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program_code{std::move(program_code)}, registry{stage, GetEngine(system, stage)},
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program_code{std::move(program_code)}, registry{stage, GetEngine(system, stage)},
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shader_ir{this->program_code, stage, main_offset, compiler_settings, registry},
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shader_ir{this->program_code, main_offset, compiler_settings, registry},
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entries{GenerateShaderEntries(shader_ir)} {}
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entries{GenerateShaderEntries(shader_ir)} {}
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CachedShader::~CachedShader() = default;
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CachedShader::~CachedShader() = default;
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@ -271,6 +271,40 @@ std::size_t GetImageTypeNumCoordinates(Tegra::Shader::ImageType image_type) {
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}
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}
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} // Anonymous namespace
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} // Anonymous namespace
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Node ShaderIR::GetComponentValue(ComponentType component_type, u32 component_size,
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const Node original_value, bool* is_signed) {
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switch (component_type) {
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case ComponentType::SNORM: {
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*is_signed = true;
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// range [-1.0, 1.0]
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auto cnv_value = Operation(OperationCode::FMul, original_value,
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Immediate((1 << component_size) / 2.f - 1.f));
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cnv_value = SignedOperation(OperationCode::ICastFloat, is_signed, std::move(cnv_value));
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return BitfieldExtract(std::move(cnv_value), 0, component_size);
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}
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case ComponentType::SINT:
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case ComponentType::UNORM: {
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*is_signed = component_type == ComponentType::SINT;
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// range [0.0, 1.0]
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auto cnv_value =
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Operation(OperationCode::FMul, original_value, Immediate((1 << component_size) - 1.f));
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return SignedOperation(OperationCode::ICastFloat, is_signed, std::move(cnv_value));
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}
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case ComponentType::UINT: // range [0, (1 << component_size) - 1]
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*is_signed = false;
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return original_value;
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case ComponentType::FLOAT:
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if (component_size == 16) {
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return Operation(OperationCode::HCastFloat, original_value);
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} else {
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return original_value;
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}
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default:
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UNIMPLEMENTED_MSG("Unimplement component type={}", component_type);
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return original_value;
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}
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}
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u32 ShaderIR::DecodeImage(NodeBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeImage(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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const auto opcode = OpCode::Decode(instr);
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@ -309,7 +343,8 @@ u32 ShaderIR::DecodeImage(NodeBlock& bb, u32 pc) {
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
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}
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}
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} else if (instr.suldst.mode == Tegra::Shader::SurfaceDataMode::D_BA) {
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} else if (instr.suldst.mode == Tegra::Shader::SurfaceDataMode::D_BA) {
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UNIMPLEMENTED_IF(instr.suldst.GetStoreDataLayout() != StoreType::Bits32);
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UNIMPLEMENTED_IF(instr.suldst.GetStoreDataLayout() != StoreType::Bits32 &&
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instr.suldst.GetStoreDataLayout() != StoreType::Bits64);
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auto descriptor = [this, instr] {
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auto descriptor = [this, instr] {
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std::optional<Tegra::Engines::SamplerDescriptor> descriptor;
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std::optional<Tegra::Engines::SamplerDescriptor> descriptor;
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@ -333,7 +368,6 @@ u32 ShaderIR::DecodeImage(NodeBlock& bb, u32 pc) {
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switch (instr.suldst.GetStoreDataLayout()) {
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switch (instr.suldst.GetStoreDataLayout()) {
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case StoreType::Bits32: {
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case StoreType::Bits32: {
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u32 shifted_counter = 0;
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u32 shifted_counter = 0;
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// value should be RGBA format
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Node value = Immediate(0);
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Node value = Immediate(0);
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for (u32 element = 0; element < 4; ++element) {
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for (u32 element = 0; element < 4; ++element) {
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if (!IsComponentEnabled(comp_mask, element)) {
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if (!IsComponentEnabled(comp_mask, element)) {
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@ -343,39 +377,12 @@ u32 ShaderIR::DecodeImage(NodeBlock& bb, u32 pc) {
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const auto component_size = GetComponentSize(descriptor.format, element);
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const auto component_size = GetComponentSize(descriptor.format, element);
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bool is_signed = true;
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bool is_signed = true;
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MetaImage meta{image, {}, element};
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MetaImage meta{image, {}, element};
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const Node original_value =
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Operation(OperationCode::ImageLoad, meta, GetCoordinates(type));
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Node converted_value = [&] {
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Node converted_value = GetComponentValue(
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switch (component_type) {
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component_type, component_size,
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case ComponentType::SNORM: {
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Operation(OperationCode::ImageLoad, meta, GetCoordinates(type)),
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is_signed = true;
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&is_signed);
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// range [-1.0, 1.0]
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auto cnv_value =
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Operation(OperationCode::FMul, original_value, Immediate(127.f));
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cnv_value = SignedOperation(OperationCode::ICastFloat, is_signed,
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std::move(cnv_value));
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return BitfieldExtract(std::move(cnv_value), 0, 8);
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}
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case ComponentType::SINT:
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case ComponentType::UNORM: {
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is_signed = false;
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// range [0.0, 1.0]
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auto cnv_value =
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Operation(OperationCode::FMul, original_value, Immediate(255.f));
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return SignedOperation(OperationCode::ICastFloat, is_signed,
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std::move(cnv_value));
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}
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case ComponentType::UINT: // range [0, 255]
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is_signed = false;
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return original_value;
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case ComponentType::FLOAT:
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return original_value;
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default:
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UNIMPLEMENTED_MSG("Unimplement component type={}", component_type);
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return original_value;
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}
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}();
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// shift element to correct position
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// shift element to correct position
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const auto shifted = shifted_counter;
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const auto shifted = shifted_counter;
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if (shifted > 0) {
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if (shifted > 0) {
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@ -391,6 +398,56 @@ u32 ShaderIR::DecodeImage(NodeBlock& bb, u32 pc) {
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SetRegister(bb, instr.gpr0.Value(), std::move(value));
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SetRegister(bb, instr.gpr0.Value(), std::move(value));
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break;
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break;
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}
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}
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case StoreType::Bits64: {
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u32 indexer = 0;
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u32 shifted_counter = 0;
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Node value = Immediate(0);
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for (u32 element = 0; element < 4; ++element) {
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if (!IsComponentEnabled(comp_mask, element)) {
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continue;
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}
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const auto component_type = GetComponentType(descriptor, element);
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const auto component_size = GetComponentSize(descriptor.format, element);
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bool is_signed = true;
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MetaImage meta{image, {}, element};
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Node converted_value = GetComponentValue(
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component_type, component_size,
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Operation(OperationCode::ImageLoad, meta, GetCoordinates(type)),
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&is_signed);
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// shift element to correct position
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const auto shifted = shifted_counter;
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if (shifted > 0) {
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converted_value =
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SignedOperation(OperationCode::ILogicalShiftLeft, is_signed,
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std::move(converted_value), Immediate(shifted));
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}
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shifted_counter += component_size;
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// add value into result
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value = Operation(OperationCode::UBitwiseOr, value, std::move(converted_value));
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// if we shifted enough for 1 byte -> we save it into temp
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if (shifted_counter >= 32) {
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SetTemporary(bb, indexer++, std::move(value));
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// we only use 2 bytes for bits64
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if (indexer >= 2) {
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break;
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}
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// reset counter and value to prepare pack next byte
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value = Immediate(0);
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shifted_counter = 0;
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}
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}
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for (u32 i = 0; i < indexer; ++i) {
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
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}
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break;
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}
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default:
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default:
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UNREACHABLE();
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UNREACHABLE();
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break;
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break;
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@ -24,10 +24,9 @@ using Tegra::Shader::PredCondition;
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using Tegra::Shader::PredOperation;
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using Tegra::Shader::PredOperation;
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using Tegra::Shader::Register;
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using Tegra::Shader::Register;
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ShaderIR::ShaderIR(const ProgramCode& program_code, Tegra::Engines::ShaderType shader_stage,
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ShaderIR::ShaderIR(const ProgramCode& program_code, u32 main_offset, CompilerSettings settings,
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u32 main_offset, CompilerSettings settings, Registry& registry)
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Registry& registry)
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: program_code{program_code}, shader_stage{shader_stage},
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: program_code{program_code}, main_offset{main_offset}, settings{settings}, registry{registry} {
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main_offset{main_offset}, settings{settings}, registry{registry} {
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Decode();
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Decode();
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PostDecode();
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PostDecode();
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}
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}
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@ -68,8 +68,8 @@ struct GlobalMemoryUsage {
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class ShaderIR final {
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class ShaderIR final {
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public:
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public:
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explicit ShaderIR(const ProgramCode& program_code, Tegra::Engines::ShaderType shader_stage,
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explicit ShaderIR(const ProgramCode& program_code, u32 main_offset, CompilerSettings settings,
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u32 main_offset, CompilerSettings settings, Registry& registry);
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Registry& registry);
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~ShaderIR();
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~ShaderIR();
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const std::map<u32, NodeBlock>& GetBasicBlocks() const {
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const std::map<u32, NodeBlock>& GetBasicBlocks() const {
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@ -312,6 +312,10 @@ private:
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/// Conditionally saturates a half float pair
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/// Conditionally saturates a half float pair
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Node GetSaturatedHalfFloat(Node value, bool saturate = true);
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Node GetSaturatedHalfFloat(Node value, bool saturate = true);
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/// Get image component value by type and size
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Node GetComponentValue(Tegra::Texture::ComponentType component_type, u32 component_size,
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const Node original_value, bool* is_signed);
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/// Returns a predicate comparing two floats
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/// Returns a predicate comparing two floats
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Node GetPredicateComparisonFloat(Tegra::Shader::PredCondition condition, Node op_a, Node op_b);
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Node GetPredicateComparisonFloat(Tegra::Shader::PredCondition condition, Node op_a, Node op_b);
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/// Returns a predicate comparing two integers
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/// Returns a predicate comparing two integers
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@ -419,7 +423,6 @@ private:
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u32 NewCustomVariable();
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u32 NewCustomVariable();
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const ProgramCode& program_code;
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const ProgramCode& program_code;
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const Tegra::Engines::ShaderType shader_stage;
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const u32 main_offset;
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const u32 main_offset;
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const CompilerSettings settings;
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const CompilerSettings settings;
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Registry& registry;
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Registry& registry;
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