mirror of
https://github.com/yuzu-mirror/yuzu.git
synced 2024-11-17 20:27:32 +01:00
gl_shader_decompiler: Implement SHR instruction.
This commit is contained in:
parent
83517cb53a
commit
5440b9c634
@ -259,6 +259,10 @@ union Instruction {
|
||||
}
|
||||
} alu;
|
||||
|
||||
union {
|
||||
BitField<48, 1, u64> is_signed;
|
||||
} shift;
|
||||
|
||||
union {
|
||||
BitField<39, 5, u64> shift_amount;
|
||||
BitField<48, 1, u64> negate_b;
|
||||
|
@ -973,6 +973,19 @@ private:
|
||||
}
|
||||
|
||||
switch (opcode->GetId()) {
|
||||
case OpCode::Id::SHR_C:
|
||||
case OpCode::Id::SHR_R:
|
||||
case OpCode::Id::SHR_IMM: {
|
||||
if (!instr.shift.is_signed) {
|
||||
// Logical shift right
|
||||
op_a = "uint(" + op_a + ')';
|
||||
}
|
||||
|
||||
// Cast to int is superfluous for arithmetic shift, it's only for a logical shift
|
||||
regs.SetRegisterToInteger(instr.gpr0, true, 0, "int(" + op_a + " >> " + op_b + ')',
|
||||
1, 1);
|
||||
break;
|
||||
}
|
||||
case OpCode::Id::SHL_C:
|
||||
case OpCode::Id::SHL_R:
|
||||
case OpCode::Id::SHL_IMM:
|
||||
|
Loading…
Reference in New Issue
Block a user