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shader_decode: Implement FMNMX_C, FMNMX_R and FMNMX_IMM
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@ -122,6 +122,24 @@ u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) {
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SetRegister(bb, instr.gpr0, value);
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SetRegister(bb, instr.gpr0, value);
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break;
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break;
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}
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}
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case OpCode::Id::FMNMX_C:
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case OpCode::Id::FMNMX_R:
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case OpCode::Id::FMNMX_IMM: {
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in FMNMX is not implemented");
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op_a = GetOperandAbsNegFloat(op_a, instr.alu.abs_a, instr.alu.negate_a);
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op_b = GetOperandAbsNegFloat(op_b, instr.alu.abs_b, instr.alu.negate_b);
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const Node condition = GetPredicate(instr.alu.fmnmx.pred, instr.alu.fmnmx.negate_pred != 0);
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const Node min = Operation(OperationCode::FMin, NO_PRECISE, op_a, op_b);
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const Node max = Operation(OperationCode::FMax, NO_PRECISE, op_a, op_b);
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SetRegister(bb, instr.gpr0,
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Operation(OperationCode::Select, NO_PRECISE, condition, min, max));
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break;
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}
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default:
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default:
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UNIMPLEMENTED_MSG("Unhandled arithmetic instruction: {}", opcode->get().GetName());
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UNIMPLEMENTED_MSG("Unhandled arithmetic instruction: {}", opcode->get().GetName());
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}
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}
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