From a80d93685af509a58315c4ad41aafe19f59d75af Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Tue, 24 Mar 2015 11:30:54 -0400
Subject: [PATCH] dyncom: Implement SRS
---
.../arm/dyncom/arm_dyncom_interpreter.cpp | 33 ++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index a1a3119a5..2765cb36e 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -2585,7 +2585,23 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index)
inst_base->load_r15 = 1;
return inst_base;
}
-static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SRS"); }
+
+static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index)
+{
+ arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
+ ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
+
+ inst_base->cond = AL;
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ inst_cream->inst = inst;
+ inst_cream->get_addr = get_calc_addr_op(inst);
+
+ return inst_base;
+}
+
static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index)
{
arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst));
@@ -5963,6 +5979,21 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
}
SRS_INST:
+ {
+ // SRS is unconditional
+ ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
+
+ u32 address = 0;
+ inst_cream->get_addr(cpu, inst_cream->inst, address, 1);
+
+ WriteMemory32(cpu, address + 0, cpu->Reg[14]);
+ WriteMemory32(cpu, address + 4, cpu->Spsr_copy);
+
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC(sizeof(ldst_inst));
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
SSAT_INST:
{