mirror of
https://github.com/yuzu-mirror/yuzu.git
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commit
ba0bfe7d82
2
externals/nihstro
vendored
2
externals/nihstro
vendored
@ -1 +1 @@
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Subproject commit 4a78588b308564f7ebae193e0ae00d9a0d5741d5
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Subproject commit 81f1804a43f625e3a1a20752c0db70a413410380
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@ -226,7 +226,8 @@ struct Regs {
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Texture1 = 0x4,
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Texture2 = 0x5,
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Texture3 = 0x6,
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// 0x7-0xc = primary color??
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PreviousBuffer = 0xd,
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Constant = 0xe,
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Previous = 0xf,
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};
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@ -299,7 +300,18 @@ struct Regs {
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BitField<24, 8, u32> const_a;
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};
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INSERT_PADDING_WORDS(0x1);
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union {
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BitField< 0, 2, u32> color_scale;
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BitField<16, 2, u32> alpha_scale;
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};
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inline unsigned GetColorMultiplier() const {
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return (color_scale < 3) ? (1 << color_scale) : 1;
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}
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inline unsigned GetAlphaMultiplier() const {
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return (alpha_scale < 3) ? (1 << alpha_scale) : 1;
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}
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};
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TevStageConfig tev_stage0;
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@ -309,11 +321,36 @@ struct Regs {
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TevStageConfig tev_stage2;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage3;
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INSERT_PADDING_WORDS(0x13);
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INSERT_PADDING_WORDS(0x3);
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union {
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// Tev stages 0-3 write their output to the combiner buffer if the corresponding bit in
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// these masks are set
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BitField< 8, 4, u32> update_mask_rgb;
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BitField<12, 4, u32> update_mask_a;
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bool TevStageUpdatesCombinerBufferColor(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_rgb & (1 << stage_index));
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}
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bool TevStageUpdatesCombinerBufferAlpha(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_a & (1 << stage_index));
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}
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} tev_combiner_buffer_input;
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INSERT_PADDING_WORDS(0xf);
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TevStageConfig tev_stage4;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage5;
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INSERT_PADDING_WORDS(0x3);
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union {
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BitField< 0, 8, u32> r;
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BitField< 8, 8, u32> g;
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BitField<16, 8, u32> b;
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BitField<24, 8, u32> a;
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} tev_combiner_buffer_color;
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INSERT_PADDING_WORDS(0x2);
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const std::array<Regs::TevStageConfig,6> GetTevStages() const {
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return { tev_stage0, tev_stage1,
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@ -426,9 +463,7 @@ struct Regs {
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D24S8 = 3
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};
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/*
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* Returns the number of bytes in the specified depth format
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*/
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// Returns the number of bytes in the specified depth format
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static u32 BytesPerDepthPixel(DepthFormat format) {
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switch (format) {
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case DepthFormat::D16:
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@ -443,6 +478,20 @@ struct Regs {
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}
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}
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// Returns the number of bits per depth component of the specified depth format
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static u32 DepthBitsPerPixel(DepthFormat format) {
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switch (format) {
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case DepthFormat::D16:
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return 16;
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case DepthFormat::D24:
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case DepthFormat::D24S8:
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return 24;
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default:
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LOG_CRITICAL(HW_GPU, "Unknown depth format %u", format);
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UNIMPLEMENTED();
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}
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}
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struct {
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// Components are laid out in reverse byte order, most significant bits first.
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enum ColorFormat : u32 {
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@ -784,8 +833,10 @@ struct Regs {
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ADD_FIELD(tev_stage1);
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ADD_FIELD(tev_stage2);
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ADD_FIELD(tev_stage3);
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ADD_FIELD(tev_combiner_buffer_input);
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ADD_FIELD(tev_stage4);
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ADD_FIELD(tev_stage5);
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ADD_FIELD(tev_combiner_buffer_color);
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ADD_FIELD(output_merger);
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ADD_FIELD(framebuffer);
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ADD_FIELD(vertex_attributes);
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@ -859,8 +910,10 @@ ASSERT_REG_POSITION(tev_stage0, 0xc0);
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ASSERT_REG_POSITION(tev_stage1, 0xc8);
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ASSERT_REG_POSITION(tev_stage2, 0xd0);
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ASSERT_REG_POSITION(tev_stage3, 0xd8);
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ASSERT_REG_POSITION(tev_combiner_buffer_input, 0xe0);
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ASSERT_REG_POSITION(tev_stage4, 0xf0);
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ASSERT_REG_POSITION(tev_stage5, 0xf8);
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ASSERT_REG_POSITION(tev_combiner_buffer_color, 0xfd);
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ASSERT_REG_POSITION(output_merger, 0x100);
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ASSERT_REG_POSITION(framebuffer, 0x110);
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ASSERT_REG_POSITION(vertex_attributes, 0x200);
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@ -90,7 +90,7 @@ static const Math::Vec4<u8> GetPixel(int x, int y) {
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UNIMPLEMENTED();
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}
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return {};
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return {0, 0, 0, 0};
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}
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static u32 GetDepth(int x, int y) {
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@ -376,7 +376,13 @@ static void ProcessTriangleInternal(const VertexShader::OutputVertex& v0,
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// with some basic arithmetic. Alpha combiners can be configured separately but work
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// analogously.
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Math::Vec4<u8> combiner_output;
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for (const auto& tev_stage : tev_stages) {
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Math::Vec4<u8> combiner_buffer = {
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registers.tev_combiner_buffer_color.r, registers.tev_combiner_buffer_color.g,
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registers.tev_combiner_buffer_color.b, registers.tev_combiner_buffer_color.a
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};
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for (unsigned tev_stage_index = 0; tev_stage_index < tev_stages.size(); ++tev_stage_index) {
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const auto& tev_stage = tev_stages[tev_stage_index];
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using Source = Regs::TevStageConfig::Source;
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using ColorModifier = Regs::TevStageConfig::ColorModifier;
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using AlphaModifier = Regs::TevStageConfig::AlphaModifier;
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@ -398,6 +404,9 @@ static void ProcessTriangleInternal(const VertexShader::OutputVertex& v0,
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case Source::Texture2:
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return texture_color[2];
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case Source::PreviousBuffer:
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return combiner_buffer;
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case Source::Constant:
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return {tev_stage.const_r, tev_stage.const_g, tev_stage.const_b, tev_stage.const_a};
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@ -407,7 +416,7 @@ static void ProcessTriangleInternal(const VertexShader::OutputVertex& v0,
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default:
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LOG_ERROR(HW_GPU, "Unknown color combiner source %d\n", (int)source);
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UNIMPLEMENTED();
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return {};
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return {0, 0, 0, 0};
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}
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};
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@ -490,6 +499,16 @@ static void ProcessTriangleInternal(const VertexShader::OutputVertex& v0,
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return result.Cast<u8>();
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}
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case Operation::AddSigned:
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{
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// TODO(bunnei): Verify that the color conversion from (float) 0.5f to (byte) 128 is correct
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auto result = input[0].Cast<int>() + input[1].Cast<int>() - Math::MakeVec<int>(128, 128, 128);
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result.r() = MathUtil::Clamp<int>(result.r(), 0, 255);
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result.g() = MathUtil::Clamp<int>(result.g(), 0, 255);
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result.b() = MathUtil::Clamp<int>(result.b(), 0, 255);
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return result.Cast<u8>();
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}
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case Operation::Lerp:
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return ((input[0] * input[2] + input[1] * (Math::MakeVec<u8>(255, 255, 255) - input[2]).Cast<u8>()) / 255).Cast<u8>();
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@ -524,7 +543,7 @@ static void ProcessTriangleInternal(const VertexShader::OutputVertex& v0,
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default:
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LOG_ERROR(HW_GPU, "Unknown color combiner operation %d\n", (int)op);
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UNIMPLEMENTED();
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return {};
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return {0, 0, 0};
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}
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};
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@ -578,7 +597,20 @@ static void ProcessTriangleInternal(const VertexShader::OutputVertex& v0,
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};
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auto alpha_output = AlphaCombine(tev_stage.alpha_op, alpha_result);
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combiner_output = Math::MakeVec(color_output, alpha_output);
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combiner_output[0] = std::min((unsigned)255, color_output.r() * tev_stage.GetColorMultiplier());
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combiner_output[1] = std::min((unsigned)255, color_output.g() * tev_stage.GetColorMultiplier());
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combiner_output[2] = std::min((unsigned)255, color_output.b() * tev_stage.GetColorMultiplier());
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combiner_output[3] = std::min((unsigned)255, alpha_output * tev_stage.GetAlphaMultiplier());
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if (registers.tev_combiner_buffer_input.TevStageUpdatesCombinerBufferColor(tev_stage_index)) {
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combiner_buffer.r() = combiner_output.r();
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combiner_buffer.g() = combiner_output.g();
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combiner_buffer.b() = combiner_output.b();
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}
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if (registers.tev_combiner_buffer_input.TevStageUpdatesCombinerBufferAlpha(tev_stage_index)) {
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combiner_buffer.a() = combiner_output.a();
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}
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}
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if (registers.output_merger.alpha_test.enable) {
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@ -624,9 +656,10 @@ static void ProcessTriangleInternal(const VertexShader::OutputVertex& v0,
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// TODO: Does depth indeed only get written even if depth testing is enabled?
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if (registers.output_merger.depth_test_enable) {
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u16 z = (u16)((v0.screenpos[2].ToFloat32() * w0 +
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v1.screenpos[2].ToFloat32() * w1 +
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v2.screenpos[2].ToFloat32() * w2) * 65535.f / wsum);
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unsigned num_bits = Pica::Regs::DepthBitsPerPixel(registers.framebuffer.depth_format);
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u32 z = (u32)((v0.screenpos[2].ToFloat32() * w0 +
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v1.screenpos[2].ToFloat32() * w1 +
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v2.screenpos[2].ToFloat32() * w2) * ((1 << num_bits) - 1) / wsum);
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u32 ref_z = GetDepth(x >> 4, y >> 4);
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bool pass = false;
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break;
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}
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case OpCode::Id::FLR:
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = float24::FromFloat32(std::floor(src1[i].ToFloat32()));
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}
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break;
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case OpCode::Id::MAX:
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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@ -366,12 +375,15 @@ static void ProcessShaderCode(VertexShaderState& state) {
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case OpCode::Type::MultiplyAdd:
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{
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if (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MAD) {
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if ((instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MAD) ||
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(instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MADI)) {
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const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.mad.operand_desc_id];
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const float24* src1_ = LookupSourceRegister(instr.mad.src1);
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const float24* src2_ = LookupSourceRegister(instr.mad.src2);
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const float24* src3_ = LookupSourceRegister(instr.mad.src3);
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bool is_inverted = (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MADI);
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const float24* src1_ = LookupSourceRegister(instr.mad.GetSrc1(is_inverted));
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const float24* src2_ = LookupSourceRegister(instr.mad.GetSrc2(is_inverted));
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const float24* src3_ = LookupSourceRegister(instr.mad.GetSrc3(is_inverted));
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const bool negate_src1 = ((bool)swizzle.negate_src1 != false);
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const bool negate_src2 = ((bool)swizzle.negate_src2 != false);
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