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shader: Implement BFE and BFI CC

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Fix two bugs in BFI.
This commit is contained in:
ameerj 2021-04-17 00:48:35 -04:00
parent 80940b1706
commit be431f5ed0
3 changed files with 17 additions and 14 deletions
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3
src/shader_recompiler/backend/spirv/emit_spirv_select.cpp
View File

@ -10,8 +10,7 @@ Id EmitSelectU1(EmitContext& ctx, Id cond, Id true_value, Id false_value) {
return ctx.OpSelect(ctx.U1, cond, true_value, false_value);
}
Id EmitSelectU8([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Id cond,
[[maybe_unused]] Id true_value, [[maybe_unused]] Id false_value) {
Id EmitSelectU8(EmitContext&, Id, Id, Id) {
throw NotImplementedException("SPIR-V Instruction");
}

11
src/shader_recompiler/frontend/maxwell/translate/impl/bitfield_extract.cpp
View File

@ -18,10 +18,6 @@ void BFE(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
BitField<48, 1, u64> is_signed;
} const bfe{insn};
if (bfe.cc != 0) {
throw NotImplementedException("BFE CC");
}
const IR::U32 offset{v.ir.BitFieldExtract(src, v.ir.Imm32(0), v.ir.Imm32(8), false)};
const IR::U32 count{v.ir.BitFieldExtract(src, v.ir.Imm32(8), v.ir.Imm32(8), false)};
@ -53,6 +49,13 @@ void BFE(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
result = IR::U32{v.ir.Select(zero_count, zero, result)};
v.X(bfe.dest_reg, result);
if (bfe.cc != 0) {
v.SetZFlag(v.ir.IEqual(result, zero));
v.SetSFlag(v.ir.ILessThan(result, zero, true));
v.ResetCFlag();
v.ResetOFlag();
}
}
} // Anonymous namespace

17
src/shader_recompiler/frontend/maxwell/translate/impl/bitfield_insert.cpp
View File

@ -16,18 +16,14 @@ void BFI(TranslatorVisitor& v, u64 insn, const IR::U32& src_a, const IR::U32& ba
BitField<47, 1, u64> cc;
} const bfi{insn};
if (bfi.cc != 0) {
throw NotImplementedException("BFI CC");
}
const IR::U32 offset{v.ir.BitFieldExtract(src_a, v.ir.Imm32(0), v.ir.Imm32(8), false)};
const IR::U32 zero{v.ir.Imm32(0)};
const IR::U32 offset{v.ir.BitFieldExtract(src_a, zero, v.ir.Imm32(8), false)};
const IR::U32 unsafe_count{v.ir.BitFieldExtract(src_a, v.ir.Imm32(8), v.ir.Imm32(8), false)};
const IR::U32 max_size{v.ir.Imm32(32)};
// Edge case conditions
const IR::U1 zero_offset{v.ir.IEqual(offset, v.ir.Imm32(0))};
const IR::U1 exceed_offset{v.ir.IGreaterThanEqual(offset, max_size, false)};
const IR::U1 exceed_count{v.ir.IGreaterThanEqual(unsafe_count, max_size, false)};
const IR::U1 exceed_count{v.ir.IGreaterThan(unsafe_count, max_size, false)};
const IR::U32 remaining_size{v.ir.ISub(max_size, offset)};
const IR::U32 safe_count{v.ir.Select(exceed_count, remaining_size, unsafe_count)};
@ -36,9 +32,14 @@ void BFI(TranslatorVisitor& v, u64 insn, const IR::U32& src_a, const IR::U32& ba
IR::U32 result{v.ir.BitFieldInsert(base, insert, offset, safe_count)};
result = IR::U32{v.ir.Select(exceed_offset, base, result)};
result = IR::U32{v.ir.Select(zero_offset, base, result)};
v.X(bfi.dest_reg, result);
if (bfi.cc != 0) {
v.SetZFlag(v.ir.IEqual(result, zero));
v.SetSFlag(v.ir.ILessThan(result, zero, true));
v.ResetCFlag();
v.ResetOFlag();
}
}
} // Anonymous namespace