mirror of
https://github.com/yuzu-mirror/yuzu.git
synced 2024-11-18 11:27:33 +01:00
shader: Implement SHR
This commit is contained in:
parent
8810c88b7e
commit
cc55d28949
@ -72,6 +72,7 @@ add_library(shader_recompiler STATIC
|
||||
frontend/maxwell/translate/impl/integer_scaled_add.cpp
|
||||
frontend/maxwell/translate/impl/integer_set_predicate.cpp
|
||||
frontend/maxwell/translate/impl/integer_shift_left.cpp
|
||||
frontend/maxwell/translate/impl/integer_shift_right.cpp
|
||||
frontend/maxwell/translate/impl/integer_short_multiply_add.cpp
|
||||
frontend/maxwell/translate/impl/load_store_attribute.cpp
|
||||
frontend/maxwell/translate/impl/load_store_memory.cpp
|
||||
|
@ -219,14 +219,15 @@ Id EmitIMul32(EmitContext& ctx, Id a, Id b);
|
||||
Id EmitINeg32(EmitContext& ctx, Id value);
|
||||
Id EmitIAbs32(EmitContext& ctx, Id value);
|
||||
Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
|
||||
void EmitShiftRightLogical32(EmitContext& ctx);
|
||||
void EmitShiftRightArithmetic32(EmitContext& ctx);
|
||||
Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b);
|
||||
Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b);
|
||||
Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b);
|
||||
Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b);
|
||||
Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b);
|
||||
Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count);
|
||||
Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count);
|
||||
Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
|
||||
Id EmitBitReverse32(EmitContext& ctx, Id value);
|
||||
Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
|
||||
Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs);
|
||||
Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs);
|
||||
|
@ -70,12 +70,12 @@ Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
|
||||
return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
|
||||
}
|
||||
|
||||
void EmitShiftRightLogical32(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b) {
|
||||
return ctx.OpShiftRightLogical(ctx.U32[1], a, b);
|
||||
}
|
||||
|
||||
void EmitShiftRightArithmetic32(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b) {
|
||||
return ctx.OpShiftRightArithmetic(ctx.U32[1], a, b);
|
||||
}
|
||||
|
||||
Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) {
|
||||
@ -102,6 +102,10 @@ Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) {
|
||||
return ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count);
|
||||
}
|
||||
|
||||
Id EmitBitReverse32(EmitContext& ctx, Id value) {
|
||||
return ctx.OpBitReverse(ctx.U32[1], value);
|
||||
}
|
||||
|
||||
Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
|
||||
return ctx.OpSLessThan(ctx.U1, lhs, rhs);
|
||||
}
|
||||
|
@ -804,6 +804,10 @@ U32 IREmitter::BitFieldExtract(const U32& base, const U32& offset, const U32& co
|
||||
count);
|
||||
}
|
||||
|
||||
U32 IREmitter::BitReverse(const U32& value) {
|
||||
return Inst<U32>(Opcode::BitReverse32, value);
|
||||
}
|
||||
|
||||
U1 IREmitter::ILessThan(const U32& lhs, const U32& rhs, bool is_signed) {
|
||||
return Inst<U1>(is_signed ? Opcode::SLessThan : Opcode::ULessThan, lhs, rhs);
|
||||
}
|
||||
|
@ -159,6 +159,7 @@ public:
|
||||
const U32& count);
|
||||
[[nodiscard]] U32 BitFieldExtract(const U32& base, const U32& offset, const U32& count,
|
||||
bool is_signed);
|
||||
[[nodiscard]] U32 BitReverse(const U32& value);
|
||||
|
||||
[[nodiscard]] U1 ILessThan(const U32& lhs, const U32& rhs, bool is_signed);
|
||||
[[nodiscard]] U1 IEqual(const U32& lhs, const U32& rhs);
|
||||
|
@ -231,6 +231,7 @@ OPCODE(BitwiseXor32, U32, U32,
|
||||
OPCODE(BitFieldInsert, U32, U32, U32, U32, U32, )
|
||||
OPCODE(BitFieldSExtract, U32, U32, U32, U32, )
|
||||
OPCODE(BitFieldUExtract, U32, U32, U32, U32, )
|
||||
OPCODE(BitReverse32, U32, U32, )
|
||||
|
||||
OPCODE(SLessThan, U1, U32, U32, )
|
||||
OPCODE(ULessThan, U1, U32, U32, )
|
||||
|
@ -0,0 +1,62 @@
|
||||
// Copyright 2021 yuzu Emulator Project
|
||||
// Licensed under GPLv2 or any later version
|
||||
// Refer to the license.txt file included.
|
||||
|
||||
#include "common/bit_field.h"
|
||||
#include "common/common_types.h"
|
||||
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
|
||||
|
||||
namespace Shader::Maxwell {
|
||||
namespace {
|
||||
void SHR(TranslatorVisitor& v, u64 insn, const IR::U32& shift) {
|
||||
union {
|
||||
u64 insn;
|
||||
BitField<0, 8, IR::Reg> dest_reg;
|
||||
BitField<8, 8, IR::Reg> src_reg_a;
|
||||
BitField<39, 1, u64> is_wrapped;
|
||||
BitField<40, 1, u64> brev;
|
||||
BitField<43, 1, u64> xmode;
|
||||
BitField<48, 1, u64> is_arithmetic;
|
||||
} const shr{insn};
|
||||
|
||||
if (shr.xmode != 0) {
|
||||
throw NotImplementedException("SHR.XMODE");
|
||||
}
|
||||
|
||||
IR::U32 base{v.X(shr.src_reg_a)};
|
||||
if (shr.brev == 1) {
|
||||
base = v.ir.BitReverse(base);
|
||||
}
|
||||
IR::U32 result;
|
||||
const IR::U32 safe_shift = shr.is_wrapped == 0 ? shift : v.ir.BitwiseAnd(shift, v.ir.Imm32(31));
|
||||
if (shr.is_arithmetic == 1) {
|
||||
result = IR::U32{v.ir.ShiftRightArithmetic(base, safe_shift)};
|
||||
} else {
|
||||
result = IR::U32{v.ir.ShiftRightLogical(base, safe_shift)};
|
||||
}
|
||||
|
||||
if (shr.is_wrapped == 0) {
|
||||
const IR::U32 zero{v.ir.Imm32(0)};
|
||||
const IR::U32 safe_bits{v.ir.Imm32(32)};
|
||||
|
||||
const IR::U1 is_negative{v.ir.ILessThan(result, zero, true)};
|
||||
const IR::U1 is_safe{v.ir.ILessThan(shift, safe_bits, false)};
|
||||
const IR::U32 clamped_value{v.ir.Select(is_negative, v.ir.Imm32(-1), zero)};
|
||||
result = IR::U32{v.ir.Select(is_safe, result, clamped_value)};
|
||||
}
|
||||
v.X(shr.dest_reg, result);
|
||||
}
|
||||
} // Anonymous namespace
|
||||
|
||||
void TranslatorVisitor::SHR_reg(u64 insn) {
|
||||
SHR(*this, insn, GetReg20(insn));
|
||||
}
|
||||
|
||||
void TranslatorVisitor::SHR_cbuf(u64 insn) {
|
||||
SHR(*this, insn, GetCbuf(insn));
|
||||
}
|
||||
|
||||
void TranslatorVisitor::SHR_imm(u64 insn) {
|
||||
SHR(*this, insn, GetImm20(insn));
|
||||
}
|
||||
} // namespace Shader::Maxwell
|
@ -757,18 +757,6 @@ void TranslatorVisitor::SHFL(u64) {
|
||||
ThrowNotImplemented(Opcode::SHFL);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::SHR_reg(u64) {
|
||||
ThrowNotImplemented(Opcode::SHR_reg);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::SHR_cbuf(u64) {
|
||||
ThrowNotImplemented(Opcode::SHR_cbuf);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::SHR_imm(u64) {
|
||||
ThrowNotImplemented(Opcode::SHR_imm);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::SSY() {
|
||||
// SSY is a no-op
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user