emu-mirror/yuzu
1
0
Fork 0
mirror of https://github.com/yuzu-mirror/yuzu.git synced 2024-11-18 21:37:32 +01:00
Code Issues Packages Projects Releases Wiki Activity

shader_ir: Remove RZ and use Register::ZeroIndex instead

Browse Source
This commit is contained in:
ReinUsesLisp 2018-12-26 01:49:32 -03:00
parent 5af82a8ed4
commit d9118d324a
3 changed files with 16 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
src/video_core/shader/decode/memory.cpp
View File

@ -91,12 +91,14 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.offset + 4, index);
const Node composite =
Operation(OperationCode::Composite, op_a, op_b, GetRegister(RZ), GetRegister(RZ));
Operation(OperationCode::Composite, op_a, op_b, GetRegister(Register::ZeroIndex),
GetRegister(Register::ZeroIndex));
MetaComponents meta{{0, 1, 2, 3}};
bb.push_back(Operation(OperationCode::AssignComposite, meta, composite,
GetRegister(instr.gpr0), GetRegister(instr.gpr0.Value() + 1),
GetRegister(RZ), GetRegister(RZ)));
GetRegister(Register::ZeroIndex),
GetRegister(Register::ZeroIndex)));
break;
}
default:
@ -197,7 +199,8 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
++dest_elem;
}
std::generate(dest.begin() + dest_elem, dest.end(), [&]() { return GetRegister(RZ); });
std::generate(dest.begin() + dest_elem, dest.end(),
[&]() { return GetRegister(Register::ZeroIndex); });
bb.push_back(Operation(OperationCode::AssignComposite, std::move(meta), texture, dest[0],
dest[1], dest[2], dest[3]));
@ -255,7 +258,8 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
++dest_elem;
}
std::generate(dest.begin() + dest_elem, dest.end(), [&]() { return GetRegister(RZ); });
std::generate(dest.begin() + dest_elem, dest.end(),
[&]() { return GetRegister(Register::ZeroIndex); });
bb.push_back(Operation(OperationCode::AssignComposite, std::move(meta_components), texture,
dest[0], dest[1], dest[2], dest[3]));
@ -369,7 +373,7 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
const MetaComponents meta_composite{{0, 1, 2, 3}};
bb.push_back(Operation(OperationCode::AssignComposite, meta_composite, texture,
GetRegister(instr.gpr0), GetRegister(instr.gpr0.Value() + 1),
GetRegister(RZ), GetRegister(RZ)));
GetRegister(Register::ZeroIndex), GetRegister(Register::ZeroIndex)));
break;
}
case OpCode::Id::TLDS: {
@ -438,7 +442,8 @@ void ShaderIR::WriteTexsInstructionFloat(BasicBlock& bb, Instruction instr, Node
++meta.count;
}
std::generate(dest.begin() + meta.count, dest.end(), [&]() { return GetRegister(RZ); });
std::generate(dest.begin() + meta.count, dest.end(),
[&]() { return GetRegister(Register::ZeroIndex); });
bb.push_back(Operation(OperationCode::AssignComposite, meta, texture, dest[0], dest[1], dest[2],
dest[3]));

9
src/video_core/shader/glsl_decompiler.cpp
View File

@ -22,6 +22,7 @@ using Tegra::Shader::Header;
using Tegra::Shader::IpaInterpMode;
using Tegra::Shader::IpaMode;
using Tegra::Shader::IpaSampleMode;
using Tegra::Shader::Register;
using namespace VideoCommon::Shader;
using Maxwell = Tegra::Engines::Maxwell3D::Regs;
@ -419,7 +420,7 @@ private:
} else if (const auto gpr = std::get_if<GprNode>(node)) {
const u32 index = gpr->GetIndex();
if (index == RZ) {
if (index == Register::ZeroIndex) {
return "0";
}
return GetRegister(index);
@ -728,8 +729,8 @@ private:
std::string target;
if (const auto gpr = std::get_if<GprNode>(dest)) {
if (gpr->GetIndex() == RZ) {
// Writing to RZ is a no op
if (gpr->GetIndex() == Register::ZeroIndex) {
// Writing to Register::ZeroIndex is a no op
return {};
}
target = GetRegister(gpr->GetIndex());
@ -776,7 +777,7 @@ private:
constexpr u32 composite_size = 4;
for (u32 i = 0; i < composite_size; ++i) {
const auto gpr = std::get<GprNode>(*operation[i + 1]).GetIndex();
if (gpr == RZ) {
if (gpr == Register::ZeroIndex) {
continue;
}
code.AddLine(GetRegister(gpr) + " = " + composite +

2
src/video_core/shader/shader_ir.h
View File

@ -41,8 +41,6 @@ using BasicBlock = std::vector<Node>;
constexpr u32 MAX_PROGRAM_LENGTH = 0x1000;
constexpr u32 RZ = 0xff;
enum class OperationCode {
Assign, /// (float& dest, float src) -> void
AssignComposite, /// (MetaComponents, float4 src, float&[4] dst) -> void