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Merge pull request #762 from Subv/ioctl2
GPU: Implement the NVGPU_IOCTL_CHANNEL_KICKOFF_PB ioctl2 command.
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commit
d95a1a3742
@ -42,6 +42,9 @@ u32 nvhost_gpu::ioctl(Ioctl command, const std::vector<u8>& input, std::vector<u
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if (command.cmd == NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO) {
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return SubmitGPFIFO(input, output);
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}
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if (command.cmd == NVGPU_IOCTL_CHANNEL_KICKOFF_PB) {
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return KickoffPB(input, output);
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}
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}
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UNIMPLEMENTED_MSG("Unimplemented ioctl");
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@ -127,14 +130,37 @@ u32 nvhost_gpu::SubmitGPFIFO(const std::vector<u8>& input, std::vector<u8>& outp
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IoctlSubmitGpfifo params{};
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std::memcpy(¶ms, input.data(), sizeof(IoctlSubmitGpfifo));
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LOG_WARNING(Service_NVDRV, "(STUBBED) called, gpfifo={:X}, num_entries={:X}, flags={:X}",
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params.gpfifo, params.num_entries, params.flags);
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params.address, params.num_entries, params.flags);
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auto entries = std::vector<IoctlGpfifoEntry>();
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entries.resize(params.num_entries);
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std::memcpy(&entries[0], &input.data()[sizeof(IoctlSubmitGpfifo)],
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params.num_entries * sizeof(IoctlGpfifoEntry));
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for (auto entry : entries) {
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VAddr va_addr = entry.Address();
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Tegra::GPUVAddr va_addr = entry.Address();
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Core::System::GetInstance().GPU().ProcessCommandList(va_addr, entry.sz);
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}
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params.fence_out.id = 0;
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params.fence_out.value = 0;
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std::memcpy(output.data(), ¶ms, output.size());
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return 0;
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}
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u32 nvhost_gpu::KickoffPB(const std::vector<u8>& input, std::vector<u8>& output) {
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if (input.size() < sizeof(IoctlSubmitGpfifo)) {
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UNIMPLEMENTED();
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}
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IoctlSubmitGpfifo params{};
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std::memcpy(¶ms, input.data(), sizeof(IoctlSubmitGpfifo));
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LOG_WARNING(Service_NVDRV, "(STUBBED) called, gpfifo={:X}, num_entries={:X}, flags={:X}",
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params.address, params.num_entries, params.flags);
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std::vector<IoctlGpfifoEntry> entries(params.num_entries);
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Memory::ReadBlock(params.address, entries.data(),
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params.num_entries * sizeof(IoctlGpfifoEntry));
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for (auto entry : entries) {
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Tegra::GPUVAddr va_addr = entry.Address();
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Core::System::GetInstance().GPU().ProcessCommandList(va_addr, entry.sz);
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}
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params.fence_out.id = 0;
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@ -15,6 +15,7 @@ namespace Service::Nvidia::Devices {
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class nvmap;
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constexpr u32 NVGPU_IOCTL_MAGIC('H');
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constexpr u32 NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO(0x8);
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constexpr u32 NVGPU_IOCTL_CHANNEL_KICKOFF_PB(0x1b);
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class nvhost_gpu final : public nvdevice {
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public:
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@ -158,14 +159,14 @@ private:
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BitField<31, 1, u32_le> unk2;
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};
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VAddr Address() const {
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return (static_cast<VAddr>(gpu_va_hi) << 32) | entry0;
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Tegra::GPUVAddr Address() const {
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return (static_cast<Tegra::GPUVAddr>(gpu_va_hi) << 32) | entry0;
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}
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};
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static_assert(sizeof(IoctlGpfifoEntry) == 8, "IoctlGpfifoEntry is incorrect size");
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struct IoctlSubmitGpfifo {
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u64_le gpfifo; // (ignored) pointer to gpfifo fence structs
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u64_le address; // pointer to gpfifo entry structs
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u32_le num_entries; // number of fence objects being submitted
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u32_le flags;
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IoctlFence fence_out; // returned new fence object for others to wait on
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@ -193,6 +194,7 @@ private:
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u32 AllocGPFIFOEx2(const std::vector<u8>& input, std::vector<u8>& output);
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u32 AllocateObjectContext(const std::vector<u8>& input, std::vector<u8>& output);
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u32 SubmitGPFIFO(const std::vector<u8>& input, std::vector<u8>& output);
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u32 KickoffPB(const std::vector<u8>& input, std::vector<u8>& output);
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u32 GetWaitbase(const std::vector<u8>& input, std::vector<u8>& output);
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u32 ChannelSetTimeout(const std::vector<u8>& input, std::vector<u8>& output);
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@ -101,7 +101,7 @@ NVDRV::NVDRV(std::shared_ptr<Module> nvdrv, const char* name)
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{8, &NVDRV::SetClientPID, "SetClientPID"},
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{9, nullptr, "DumpGraphicsMemoryInfo"},
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{10, nullptr, "InitializeDevtools"},
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{11, nullptr, "Ioctl2"},
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{11, &NVDRV::Ioctl, "Ioctl2"},
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{12, nullptr, "Ioctl3"},
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{13, &NVDRV::FinishInitialize, "FinishInitialize"},
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};
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