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video_core: Keep the definition of DimensionControl consistent with nvidia open doc
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@ -856,8 +856,8 @@ public:
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struct ZetaSize {
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enum class DimensionControl : u32 {
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DepthDefinesArray = 0,
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ArraySizeOne = 1,
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DefineArraySize = 0,
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ArraySizeIsOne = 1,
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};
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u32 width;
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@ -1104,8 +1104,8 @@ public:
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struct TileMode {
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enum class DimensionControl : u32 {
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DepthDefinesArray = 0,
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DepthDefinesDepth = 1,
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DefineArraySize = 0,
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DefineDepthSize = 1,
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};
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union {
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BitField<0, 4, u32> block_width;
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@ -14,6 +14,7 @@
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namespace VideoCommon {
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using Tegra::Engines::Fermi2D;
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using Tegra::Engines::Maxwell3D;
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using Tegra::Texture::TextureType;
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using Tegra::Texture::TICEntry;
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@ -114,13 +115,13 @@ ImageInfo::ImageInfo(const TICEntry& config) noexcept {
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}
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}
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ImageInfo::ImageInfo(const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig& ct,
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ImageInfo::ImageInfo(const Maxwell3D::Regs::RenderTargetConfig& ct,
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Tegra::Texture::MsaaMode msaa_mode) noexcept {
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format = VideoCore::Surface::PixelFormatFromRenderTargetFormat(ct.format);
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rescaleable = false;
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if (ct.tile_mode.is_pitch_linear) {
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ASSERT(ct.tile_mode.dim_control ==
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Maxwell3D::Regs::TileMode::DimensionControl::DepthDefinesArray);
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Maxwell3D::Regs::TileMode::DimensionControl::DefineArraySize);
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type = ImageType::Linear;
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pitch = ct.width;
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size = Extent3D{
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@ -140,8 +141,7 @@ ImageInfo::ImageInfo(const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig&
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.height = ct.tile_mode.block_height,
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.depth = ct.tile_mode.block_depth,
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};
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if (ct.tile_mode.dim_control ==
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Maxwell3D::Regs::TileMode::DimensionControl::DepthDefinesDepth) {
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if (ct.tile_mode.dim_control == Maxwell3D::Regs::TileMode::DimensionControl::DefineDepthSize) {
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type = ImageType::e3D;
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size.depth = ct.depth;
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} else {
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@ -153,8 +153,7 @@ ImageInfo::ImageInfo(const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig&
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}
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}
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ImageInfo::ImageInfo(const Tegra::Engines::Maxwell3D::Regs::Zeta& zt,
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const Tegra::Engines::Maxwell3D::Regs::ZetaSize& zt_size,
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ImageInfo::ImageInfo(const Maxwell3D::Regs::Zeta& zt, const Maxwell3D::Regs::ZetaSize& zt_size,
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Tegra::Texture::MsaaMode msaa_mode) noexcept {
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format = VideoCore::Surface::PixelFormatFromDepthFormat(zt.format);
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size.width = zt_size.width;
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@ -171,30 +170,34 @@ ImageInfo::ImageInfo(const Tegra::Engines::Maxwell3D::Regs::Zeta& zt,
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};
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if (zt.tile_mode.is_pitch_linear) {
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ASSERT(zt.tile_mode.dim_control ==
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Maxwell3D::Regs::TileMode::DimensionControl::DepthDefinesArray);
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Maxwell3D::Regs::TileMode::DimensionControl::DefineArraySize);
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type = ImageType::Linear;
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pitch = size.width * BytesPerBlock(format);
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} else if (zt.tile_mode.dim_control ==
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Maxwell3D::Regs::TileMode::DimensionControl::DepthDefinesDepth) {
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ASSERT(zt.tile_mode.is_pitch_linear == 0);
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ASSERT(zt_size.dim_control == Maxwell3D::Regs::ZetaSize::DimensionControl::ArraySizeOne);
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Maxwell3D::Regs::TileMode::DimensionControl::DefineDepthSize) {
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ASSERT(zt_size.dim_control == Maxwell3D::Regs::ZetaSize::DimensionControl::ArraySizeIsOne);
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type = ImageType::e3D;
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size.depth = zt_size.depth;
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} else {
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ASSERT(zt_size.dim_control ==
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Maxwell3D::Regs::ZetaSize::DimensionControl::DepthDefinesArray);
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rescaleable = block.depth == 0;
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downscaleable = size.height > 512;
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type = ImageType::e2D;
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resources.layers = zt_size.depth;
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switch (zt_size.dim_control) {
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case Maxwell3D::Regs::ZetaSize::DimensionControl::DefineArraySize:
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resources.layers = zt_size.depth;
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break;
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case Maxwell3D::Regs::ZetaSize::DimensionControl::ArraySizeIsOne:
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resources.layers = 1;
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break;
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}
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}
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}
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ImageInfo::ImageInfo(const Tegra::Engines::Fermi2D::Surface& config) noexcept {
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ImageInfo::ImageInfo(const Fermi2D::Surface& config) noexcept {
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UNIMPLEMENTED_IF_MSG(config.layer != 0, "Surface layer is not zero");
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format = VideoCore::Surface::PixelFormatFromRenderTargetFormat(config.format);
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rescaleable = false;
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if (config.linear == Tegra::Engines::Fermi2D::MemoryLayout::Pitch) {
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if (config.linear == Fermi2D::MemoryLayout::Pitch) {
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type = ImageType::Linear;
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size = Extent3D{
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.width = config.pitch / VideoCore::Surface::BytesPerBlock(format),
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