From 3f00d341d56ded86572e7528065def4e4f74687d Mon Sep 17 00:00:00 2001 From: PikalaxALT Date: Tue, 28 Nov 2017 19:41:32 -0500 Subject: [PATCH] nonmatching sub_800CF34 --- asm/link_rfu.s | 274 ----------------------------- include/librfu.h | 14 +- src/link_rfu.c | 438 ++++++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 427 insertions(+), 299 deletions(-) diff --git a/asm/link_rfu.s b/asm/link_rfu.s index 3c825581f..07de82aba 100644 --- a/asm/link_rfu.s +++ b/asm/link_rfu.s @@ -5,280 +5,6 @@ .text - thumb_func_start sub_800CF34 -sub_800CF34: @ 800CF34 - push {r4-r7,lr} - mov r7, r10 - mov r6, r9 - mov r5, r8 - push {r5-r7} - sub sp, 0x8 - ldr r1, =gUnknown_03004140 - ldrb r0, [r1, 0x4] - subs r0, 0x5 - lsls r0, 24 - lsrs r0, 24 - adds r3, r1, 0 - cmp r0, 0x3 - bls _0800CF52 - b _0800D146 -_0800CF52: - ldr r0, =gUnknown_03007890 - ldr r2, [r0] - ldrb r1, [r2, 0x2] - ldrb r0, [r3, 0xC] - adds r4, r1, 0 - eors r4, r0 - ands r4, r1 - ldrb r0, [r2, 0x7] - bics r4, r0 - mov r8, r4 - strb r1, [r3, 0xC] - cmp r4, 0 - beq _0800CF7A - strh r4, [r3, 0x14] - movs r0, 0x10 - movs r1, 0x1 - str r3, [sp, 0x4] - bl sub_800D30C - ldr r3, [sp, 0x4] -_0800CF7A: - movs r0, 0 - str r0, [sp] - movs r6, 0 - adds r7, r3, 0 - movs r1, 0x24 - adds r1, r3 - mov r9, r1 -_0800CF88: - movs r0, 0x80 - lsls r0, 17 - lsls r0, r6 - lsrs r4, r0, 24 - movs r5, 0 - mov r0, r8 - ands r0, r4 - cmp r0, 0 - beq _0800CFDA - lsls r1, r6, 1 - adds r0, r7, 0 - adds r0, 0x28 - adds r1, r0 - ldrh r0, [r7, 0x26] - strh r0, [r1] - mov r2, r9 - ldrb r1, [r2] - adds r0, r4, 0 - orrs r0, r1 - strb r0, [r2] - adds r6, 0x1 - mov r10, r6 - b _0800D090 - .pool -_0800CFC0: - ldrb r1, [r7] - adds r0, r4, 0 - orrs r0, r1 - strb r0, [r7] - ldrb r0, [r7, 0x1] - adds r0, 0x1 - strb r0, [r7, 0x1] - ldr r0, [sp] - orrs r0, r4 - str r0, [sp] - movs r0, 0x1 - orrs r5, r0 - b _0800D024 -_0800CFDA: - mov r1, r9 - ldrb r0, [r1] - ands r0, r4 - adds r2, r6, 0x1 - mov r10, r2 - cmp r0, 0 - beq _0800D090 - ldr r0, =gUnknown_03007880 - lsls r1, r6, 2 - adds r1, r0 - ldr r1, [r1] - ldrh r0, [r1, 0x34] - cmp r0, 0x46 - bne _0800D040 - adds r0, r1, 0 - adds r0, 0x61 - ldrb r0, [r0] - cmp r0, 0x1 - bne _0800D058 - movs r5, 0x2 - ldr r3, [r3, 0x20] - ldrh r2, [r3] - ldr r0, =0x0000ffff - cmp r2, r0 - beq _0800D024 - ldr r0, =gUnknown_03007890 - ldr r0, [r0] - lsls r1, r6, 5 - adds r0, r1 - ldrh r0, [r0, 0x18] - ldr r1, =0x0000ffff -_0800D018: - cmp r0, r2 - beq _0800CFC0 - adds r3, 0x2 - ldrh r2, [r3] - cmp r2, r1 - bne _0800D018 -_0800D024: - movs r0, 0x1 - ands r0, r5 - cmp r0, 0 - bne _0800D058 - movs r0, 0x4 - orrs r5, r0 - b _0800D058 - .pool -_0800D040: - lsls r1, r6, 1 - adds r0, r3, 0 - adds r0, 0x28 - adds r1, r0 - ldrh r0, [r1] - subs r0, 0x1 - strh r0, [r1] - ldr r1, =0x0000ffff - ands r0, r1 - cmp r0, 0 - bne _0800D058 - movs r5, 0x6 -_0800D058: - movs r0, 0x2 - ands r0, r5 - cmp r0, 0 - beq _0800D07E - mov r2, r9 - ldrb r0, [r2] - bics r0, r4 - movs r2, 0 - mov r1, r9 - strb r0, [r1] - lsls r0, r6, 1 - adds r1, r7, 0 - adds r1, 0x28 - adds r0, r1 - strh r2, [r0] - movs r0, 0x8 - adds r1, r6, 0 - bl rfu_clearSlot -_0800D07E: - movs r0, 0x4 - ands r5, r0 - ldr r3, =gUnknown_03004140 - cmp r5, 0 - beq _0800D090 - ldrb r1, [r7, 0xD] - adds r0, r4, 0 - orrs r0, r1 - strb r0, [r7, 0xD] -_0800D090: - mov r2, r10 - lsls r0, r2, 24 - lsrs r6, r0, 24 - cmp r6, 0x3 - bhi _0800D09C - b _0800CF88 -_0800D09C: - ldr r4, [sp] - cmp r4, 0 - beq _0800D0AE - ldr r0, =gUnknown_03004140 - strh r4, [r0, 0x14] - movs r0, 0x11 - movs r1, 0x1 - bl sub_800D30C -_0800D0AE: - ldr r1, =gUnknown_03004140 - ldrb r0, [r1, 0xD] - cmp r0, 0 - beq _0800D0EA - movs r5, 0x1 - ldr r0, =gUnknown_03007890 - ldr r0, [r0] - ldrb r0, [r0, 0x6] - cmp r0, 0 - beq _0800D0CE - ldrb r0, [r1, 0x3] - ldrb r1, [r1] - ands r0, r1 - cmp r0, r1 - beq _0800D0CE - movs r5, 0 -_0800D0CE: - cmp r5, 0 - beq _0800D0EA - ldr r4, =gUnknown_03004140 - ldrb r0, [r4, 0xD] - bl sub_800D334 - ldrb r0, [r4, 0xD] - movs r1, 0 - strh r0, [r4, 0x14] - strb r1, [r4, 0xD] - movs r0, 0x12 - movs r1, 0x1 - bl sub_800D30C -_0800D0EA: - ldr r0, =gUnknown_03004140 - adds r1, r0, 0 - adds r1, 0x24 - ldrb r1, [r1] - adds r3, r0, 0 - cmp r1, 0 - bne _0800D146 - ldrb r0, [r3, 0x4] - cmp r0, 0x8 - bne _0800D146 - ldrb r0, [r3, 0x7] - cmp r0, 0 - bne _0800D120 - strb r0, [r3, 0x5] - strb r0, [r3, 0x4] - movs r0, 0x14 - movs r1, 0 - bl sub_800D30C - b _0800D146 - .pool -_0800D120: - cmp r0, 0x2 - bne _0800D12C - movs r0, 0x3 - strb r0, [r3, 0x7] - movs r0, 0x9 - b _0800D132 -_0800D12C: - movs r0, 0x1 - strb r0, [r3, 0x7] - movs r0, 0x5 -_0800D132: - strb r0, [r3, 0x4] - ldrb r0, [r3] - cmp r0, 0 - beq _0800D146 - movs r0, 0 - strh r0, [r3, 0x1A] - movs r0, 0x8 - strb r0, [r3, 0x7] - movs r0, 0x5 - strb r0, [r3, 0x4] -_0800D146: - add sp, 0x8 - pop {r3-r5} - mov r8, r3 - mov r9, r4 - mov r10, r5 - pop {r4-r7} - pop {r0} - bx r0 - thumb_func_end sub_800CF34 - thumb_func_start sub_800D158 sub_800D158: @ 800D158 push {r4-r6,lr} diff --git a/include/librfu.h b/include/librfu.h index 7891f8679..05d895148 100644 --- a/include/librfu.h +++ b/include/librfu.h @@ -113,7 +113,11 @@ struct RfuUnk1 struct RfuUnk2 { - u8 unk_0[0x68]; + u8 unk_0[0x34]; + u16 unk_34; + u8 fill_36[0x2b]; + u8 unk_61; + u8 fill_62[6]; u32 unk_68; u32 unk_6c; u8 unk_70[0x70]; @@ -133,11 +137,15 @@ struct RfuUnk5 u8 unk_01; u8 unk_02; u8 unk_03; - u8 unk_04[4]; + u8 unk_04; + u8 unk_05; + u8 unk_06; + u8 unk_07; u8 unk_08; u8 filler_09[11]; u16 unk_14; - u8 filler_16[10]; + u8 filler_16[2]; + u16 unk_18[4]; }; extern struct RfuStruct *gRfuState; diff --git a/src/link_rfu.c b/src/link_rfu.c index 5beb7c88b..9f06e9141 100644 --- a/src/link_rfu.c +++ b/src/link_rfu.c @@ -68,7 +68,7 @@ u32 sub_800BEC0(void) void rfu_REQ_sendData_wrapper(u8 r2) { u8 val; - if (!gUnknown_03007890->unk_00) + if (!gUnknown_03007890[0].unk_00) { val = gUnknown_03004140.unk_02; r2 = 0; @@ -220,7 +220,7 @@ u8 sub_800C12C(u16 r6, u16 r8) sub_800D30C(0xF3, 0x01); return 2; } - for (i = 0; i < gUnknown_03007890->unk_08; i++) + for (i = 0; i < gUnknown_03007890[0].unk_08; i++) { tmp = &gUnknown_03007890[i]; if (tmp->unk_14 == r6) @@ -228,7 +228,7 @@ u8 sub_800C12C(u16 r6, u16 r8) break; } } - if (gUnknown_03007890->unk_08 == 0 || i == gUnknown_03007890->unk_08) + if (gUnknown_03007890[0].unk_08 == 0 || i == gUnknown_03007890[0].unk_08) { gUnknown_03004140.unk_14 = 3; sub_800D30C(0xF3, 0x01); @@ -267,7 +267,7 @@ void sub_800C210(u8 a0) gUnknown_03004140.unk_34[i] = 0; } } - i = gUnknown_03007890->unk_03 & a0; + i = gUnknown_03007890[0].unk_03 & a0; if (i) { sub_800D334(i); @@ -336,8 +336,8 @@ void sub_800C27C(bool8 a0) case 16: gUnknown_03004140.unk_04 = gUnknown_03004140.unk_11; gUnknown_03004140.unk_05 = gUnknown_03004140.unk_12; - sub_800D334(gUnknown_03007890->unk_03); - gUnknown_03004140.unk_14 = gUnknown_03007890->unk_03; + sub_800D334(gUnknown_03007890[0].unk_03); + gUnknown_03004140.unk_14 = gUnknown_03007890[0].unk_03; sub_800D30C(0x33, 0x01); return; case 17: @@ -409,7 +409,7 @@ bool8 sub_800C36C(u16 a0) } sub_800D610(); } - if (gUnknown_03007890->unk_00 == 1) + if (gUnknown_03007890[0].unk_00 == 1) { if (sp2) { @@ -540,7 +540,7 @@ void sub_800C54C(u32 a0) case 15: break; case 16: - rfu_REQ_CHILD_startConnectRecovery(gUnknown_03007890->unk_03); + rfu_REQ_CHILD_startConnectRecovery(gUnknown_03007890[0].unk_03); break; case 17: rfu_REQ_CHILD_pollConnectRecovery(); @@ -563,7 +563,7 @@ void sub_800C54C(u32 a0) gUnknown_03004140.unk_0e = 0; } } while (gUnknown_03004140.unk_04 == 18 || gUnknown_03004140.unk_04 == 19); - if (gUnknown_03007890->unk_00 != 1 || !sub_800C36C(0)) + if (gUnknown_03007890[0].unk_00 != 1 || !sub_800C36C(0)) { sub_800CF34(); sub_800D158(); @@ -689,7 +689,7 @@ void sub_800C7B4(u16 r8, u16 r6) { sub_800D30C(0x20, 0x01); } - if (gUnknown_03004140.unk_0b && gUnknown_03004140.unk_1a != 1 && gUnknown_03007890->unk_08 == 4) + if (gUnknown_03004140.unk_0b && gUnknown_03004140.unk_1a != 1 && gUnknown_03007890[0].unk_08 == 4) { rfu_REQ_endSearchParent(); rfu_waitREQComplete(); @@ -765,11 +765,11 @@ void sub_800C7B4(u16 r8, u16 r6) case 50: if (r6 == 0) { - gUnknown_03004140.unk_14 = gUnknown_03007890->unk_03; + gUnknown_03004140.unk_14 = gUnknown_03007890[0].unk_03; gUnknown_03004140.unk_04 = gUnknown_03004140.unk_05 = 17; for (gUnknown_03004140.unk_10 = 0; gUnknown_03004140.unk_10 < 4; gUnknown_03004140.unk_10 ++) { - if ((gUnknown_03007890->unk_03 >> gUnknown_03004140.unk_10) & 1) + if ((gUnknown_03007890[0].unk_03 >> gUnknown_03004140.unk_10) & 1) { break; } @@ -798,7 +798,7 @@ void sub_800C7B4(u16 r8, u16 r6) else { gUnknown_03004140.unk_04 = gUnknown_03004140.unk_05 = 0; - sub_800D334(gUnknown_03007890->unk_03); + sub_800D334(gUnknown_03007890[0].unk_03); gUnknown_03004140.unk_1e = 0x33; } gUnknown_03004140.unk_34[gUnknown_03004140.unk_10] = 0; @@ -832,7 +832,7 @@ void sub_800C7B4(u16 r8, u16 r6) { gUnknown_03004140.unk_04 = gUnknown_03004140.unk_05 = 0; sub_800D610(); - sub_800D334(gUnknown_03007890->unk_02 | gUnknown_03007890->unk_03); + sub_800D334(gUnknown_03007890[0].unk_02 | gUnknown_03007890[0].unk_03); gUnknown_03004140.unk_14 = sp0; sub_800D30C(0x25, 0x01); } @@ -854,10 +854,10 @@ void sub_800C7B4(u16 r8, u16 r6) rfu_REQ_RFUStatus(); rfu_waitREQComplete(); rfu_getRFUStatus(&sp0); - if (sp0 == 0 && gUnknown_03007890->unk_00 == 0) + if (sp0 == 0 && gUnknown_03007890[0].unk_00 == 0) { stwiRecvBuffer = rfu_getSTWIRecvBuffer(); - stwiRecvBuffer[4] = gUnknown_03007890->unk_02; + stwiRecvBuffer[4] = gUnknown_03007890[0].unk_02; stwiRecvBuffer[5] = 1; sub_800C36C(0x29); r6 = 0; @@ -897,7 +897,7 @@ void sub_800C7B4(u16 r8, u16 r6) gUnknown_03004140.unk_00 &= ~gUnknown_03004140.unk_14; if (gUnknown_03004140.unk_07) { - if (gUnknown_03007890->unk_00 == 0xFF) + if (gUnknown_03007890[0].unk_00 == 0xFF) { if (gUnknown_03004140.unk_07 == 8) { @@ -912,7 +912,7 @@ void sub_800C7B4(u16 r8, u16 r6) } } } - if (gUnknown_03007890->unk_00 == 0xFF) + if (gUnknown_03007890[0].unk_00 == 0xFF) { if (gUnknown_03004140.unk_04 == 0) { @@ -927,7 +927,7 @@ void sub_800C7B4(u16 r8, u16 r6) break; case 38: sub_800D20C(); - if (gUnknown_03007890->unk_00 != 0xFF) + if (gUnknown_03007890[0].unk_00 != 0xFF) { sub_800D30C(0x50, 0x00); } @@ -952,8 +952,8 @@ void sub_800C7B4(u16 r8, u16 r6) { if (r8 == 28 && r6 != 0 && gUnknown_03004140.unk_07 == 4) { - gUnknown_03007890->unk_00 = 1; - gUnknown_03007890->unk_02 = 15; + gUnknown_03007890[0].unk_00 = 1; + gUnknown_03007890[0].unk_02 = 15; sub_800D334(15); rfu_waitREQComplete(); return; @@ -985,7 +985,7 @@ void sub_800CEB0(u16 r6) r7 = gUnknown_03004140.unk_0e; gUnknown_03004140.unk_0e = 0; gUnknown_03004140.unk_0f = 1; - if (gUnknown_03007890->unk_00 == 0) + if (gUnknown_03007890[0].unk_00 == 0) { sub_800C36C(r6); if (gUnknown_03004140.unk_02 != 1) @@ -1015,3 +1015,397 @@ void sub_800CEB0(u16 r6) gUnknown_03004140.unk_0f = 0; gUnknown_03004140.unk_0e = r7; } + +#ifdef NONMATCHING +void sub_800CF34(void) +{ + u8 flags; + u8 sp0; + u8 i; + u8 r5; + u8 r4; + u16 *ptr; + + if (gUnknown_03004140.unk_04 == 5 || gUnknown_03004140.unk_04 == 6 || gUnknown_03004140.unk_04 == 7 || gUnknown_03004140.unk_04 == 8) + { + flags = ((gUnknown_03007890[0].unk_02 ^ gUnknown_03004140.unk_0c) & gUnknown_03007890[0].unk_02) & ~gUnknown_03007890[0].unk_07; + gUnknown_03004140.unk_0c = gUnknown_03007890[0].unk_02; + if (flags) + { + gUnknown_03004140.unk_14 = flags; + sub_800D30C(0x10, 0x01); + } + sp0 = 0x00; + for (i = 0; i < 4; i++) + { + r4 = 1 << i; + r5 = 0x00; + if (flags & r4) + { + gUnknown_03004140.unk_28[i] = gUnknown_03004140.unk_26; + gUnknown_03004140.unk_24 |= r4; + } + else if (gUnknown_03004140.unk_24 & r4) + { + if (gUnknown_03007880[i]->unk_34 == 0x46) + { + if (gUnknown_03007880[i]->unk_61 == 1) + { + r5 = 0x02; + for (ptr = gUnknown_03004140.unk_20; *ptr != 0xFFFF; ptr++) + { + if (*gUnknown_03007890[i].unk_18 == *ptr) // FIXME: Role of r0 and r1 is swapped + { + gUnknown_03004140.unk_00 |= r4; + gUnknown_03004140.unk_01++; + sp0 |= r4; + r5 |= 0x01; + break; + } + } + if (!(r5 & 0x01)) + { + r5 |= 0x04; + } + } + } + else if (--gUnknown_03004140.unk_28[i] == 0) + { + r5 = 0x06; + } + if (r5 & 0x02) + { + gUnknown_03004140.unk_24 &= ~r4; + gUnknown_03004140.unk_28[i] = 0; + rfu_clearSlot(0x08, i); + } + if (r5 & 0x04) + { + gUnknown_03004140.unk_0d |= r4; + } + } + } + if (sp0) + { + gUnknown_03004140.unk_14 = sp0; + sub_800D30C(0x11, 0x01); + } + if (gUnknown_03004140.unk_0d) + { + r5 = 0x01; + if (gUnknown_03007890[0].unk_06 && ((gUnknown_03004140.unk_03 & gUnknown_03004140.unk_00) != gUnknown_03004140.unk_00)) + { + r5 = 0x00; + } + if (r5) + { + sub_800D334(gUnknown_03004140.unk_0d); + gUnknown_03004140.unk_14 = gUnknown_03004140.unk_0d; + gUnknown_03004140.unk_0d = 0; + sub_800D30C(0x12, 0x01); + } + } + if (gUnknown_03004140.unk_24 == 0 && gUnknown_03004140.unk_04 == 8) + { + if (gUnknown_03004140.unk_07 == 0) + { + gUnknown_03004140.unk_04 = gUnknown_03004140.unk_05 = 0; + sub_800D30C(0x14, 0x00); + } + else + { + if (gUnknown_03004140.unk_07 == 2) + { + gUnknown_03004140.unk_07 = 3; + gUnknown_03004140.unk_04 = 9; + } + else + { + gUnknown_03004140.unk_07 = 1; + gUnknown_03004140.unk_04 = 5; + } + if (gUnknown_03004140.unk_00) + { + gUnknown_03004140.unk_1a = 0; + gUnknown_03004140.unk_07 = 8; + gUnknown_03004140.unk_04 = 5; + } + } + } + } +} +#else +__attribute__((naked)) void sub_800CF34(void) +{ + asm_unified("\tpush {r4-r7,lr}\n" + "\tmov r7, r10\n" + "\tmov r6, r9\n" + "\tmov r5, r8\n" + "\tpush {r5-r7}\n" + "\tsub sp, 0x8\n" + "\tldr r1, =gUnknown_03004140\n" + "\tldrb r0, [r1, 0x4]\n" + "\tsubs r0, 0x5\n" + "\tlsls r0, 24\n" + "\tlsrs r0, 24\n" + "\tadds r3, r1, 0\n" + "\tcmp r0, 0x3\n" + "\tbls _0800CF52\n" + "\tb _0800D146_break\n" + "_0800CF52:\n" + "\tldr r0, =gUnknown_03007890\n" + "\tldr r2, [r0]\n" + "\tldrb r1, [r2, 0x2]\n" + "\tldrb r0, [r3, 0xC]\n" + "\tadds r4, r1, 0\n" + "\teors r4, r0\n" + "\tands r4, r1\n" + "\tldrb r0, [r2, 0x7]\n" + "\tbics r4, r0\n" + "\tmov r8, r4\n" + "\tstrb r1, [r3, 0xC]\n" + "\tcmp r4, 0\n" + "\tbeq _0800CF7A\n" + "\tstrh r4, [r3, 0x14]\n" + "\tmovs r0, 0x10\n" + "\tmovs r1, 0x1\n" + "\tstr r3, [sp, 0x4]\n" + "\tbl sub_800D30C\n" + "\tldr r3, [sp, 0x4]\n" + "_0800CF7A:\n" + "\tmovs r0, 0\n" + "\tstr r0, [sp]\n" + "\tmovs r6, 0\n" + "\tadds r7, r3, 0\n" + "\tmovs r1, 0x24\n" + "\tadds r1, r3\n" + "\tmov r9, r1\n" + "_0800CF88:\n" + "\tmovs r0, 0x80\n" + "\tlsls r0, 17\n" + "\tlsls r0, r6\n" + "\tlsrs r4, r0, 24\n" + "\tmovs r5, 0\n" + "\tmov r0, r8\n" + "\tands r0, r4\n" + "\tcmp r0, 0\n" + "\tbeq _0800CFDA\n" + "\tlsls r1, r6, 1\n" + "\tadds r0, r7, 0\n" + "\tadds r0, 0x28\n" + "\tadds r1, r0\n" + "\tldrh r0, [r7, 0x26]\n" + "\tstrh r0, [r1]\n" + "\tmov r2, r9\n" + "\tldrb r1, [r2]\n" + "\tadds r0, r4, 0\n" + "\torrs r0, r1\n" + "\tstrb r0, [r2]\n" + "\tadds r6, 0x1\n" + "\tmov r10, r6\n" + "\tb _0800D090\n" + "\t.pool\n" + "_0800CFC0:\n" + "\tldrb r1, [r7]\n" + "\tadds r0, r4, 0\n" + "\torrs r0, r1\n" + "\tstrb r0, [r7]\n" + "\tldrb r0, [r7, 0x1]\n" + "\tadds r0, 0x1\n" + "\tstrb r0, [r7, 0x1]\n" + "\tldr r0, [sp]\n" + "\torrs r0, r4\n" + "\tstr r0, [sp]\n" + "\tmovs r0, 0x1\n" + "\torrs r5, r0\n" + "\tb _0800D024\n" + "_0800CFDA:\n" + "\tmov r1, r9\n" + "\tldrb r0, [r1]\n" + "\tands r0, r4\n" + "\tadds r2, r6, 0x1\n" + "\tmov r10, r2\n" + "\tcmp r0, 0\n" + "\tbeq _0800D090\n" + "\tldr r0, =gUnknown_03007880\n" + "\tlsls r1, r6, 2\n" + "\tadds r1, r0\n" + "\tldr r1, [r1]\n" + "\tldrh r0, [r1, 0x34]\n" + "\tcmp r0, 0x46\n" + "\tbne _0800D040\n" + "\tadds r0, r1, 0\n" + "\tadds r0, 0x61\n" + "\tldrb r0, [r0]\n" + "\tcmp r0, 0x1\n" + "\tbne _0800D058\n" + "\tmovs r5, 0x2\n" + "\tldr r3, [r3, 0x20]\n" + "\tldrh r2, [r3]\n" + "\tldr r0, =0x0000ffff\n" + "\tcmp r2, r0\n" + "\tbeq _0800D024\n" + "\tldr r0, =gUnknown_03007890\n" + "\tldr r0, [r0]\n" + "\tlsls r1, r6, 5\n" + "\tadds r0, r1\n" + "\tldrh r0, [r0, 0x18]\n" + "\tldr r1, =0x0000ffff\n" + "_0800D018:\n" + "\tcmp r0, r2\n" + "\tbeq _0800CFC0\n" + "\tadds r3, 0x2\n" + "\tldrh r2, [r3]\n" + "\tcmp r2, r1\n" + "\tbne _0800D018\n" + "_0800D024:\n" + "\tmovs r0, 0x1\n" + "\tands r0, r5\n" + "\tcmp r0, 0\n" + "\tbne _0800D058\n" + "\tmovs r0, 0x4\n" + "\torrs r5, r0\n" + "\tb _0800D058\n" + "\t.pool\n" + "_0800D040:\n" + "\tlsls r1, r6, 1\n" + "\tadds r0, r3, 0\n" + "\tadds r0, 0x28\n" + "\tadds r1, r0\n" + "\tldrh r0, [r1]\n" + "\tsubs r0, 0x1\n" + "\tstrh r0, [r1]\n" + "\tldr r1, =0x0000ffff\n" + "\tands r0, r1\n" + "\tcmp r0, 0\n" + "\tbne _0800D058\n" + "\tmovs r5, 0x6\n" + "_0800D058:\n" + "\tmovs r0, 0x2\n" + "\tands r0, r5\n" + "\tcmp r0, 0\n" + "\tbeq _0800D07E\n" + "\tmov r2, r9\n" + "\tldrb r0, [r2]\n" + "\tbics r0, r4\n" + "\tmovs r2, 0\n" + "\tmov r1, r9\n" + "\tstrb r0, [r1]\n" + "\tlsls r0, r6, 1\n" + "\tadds r1, r7, 0\n" + "\tadds r1, 0x28\n" + "\tadds r0, r1\n" + "\tstrh r2, [r0]\n" + "\tmovs r0, 0x8\n" + "\tadds r1, r6, 0\n" + "\tbl rfu_clearSlot\n" + "_0800D07E:\n" + "\tmovs r0, 0x4\n" + "\tands r5, r0\n" + "\tldr r3, =gUnknown_03004140\n" + "\tcmp r5, 0\n" + "\tbeq _0800D090\n" + "\tldrb r1, [r7, 0xD]\n" + "\tadds r0, r4, 0\n" + "\torrs r0, r1\n" + "\tstrb r0, [r7, 0xD]\n" + "_0800D090:\n" + "\tmov r2, r10\n" + "\tlsls r0, r2, 24\n" + "\tlsrs r6, r0, 24\n" + "\tcmp r6, 0x3\n" + "\tbhi _0800D09C\n" + "\tb _0800CF88\n" + "_0800D09C:\n" + "\tldr r4, [sp]\n" + "\tcmp r4, 0\n" + "\tbeq _0800D0AE\n" + "\tldr r0, =gUnknown_03004140\n" + "\tstrh r4, [r0, 0x14]\n" + "\tmovs r0, 0x11\n" + "\tmovs r1, 0x1\n" + "\tbl sub_800D30C\n" + "_0800D0AE:\n" + "\tldr r1, =gUnknown_03004140\n" + "\tldrb r0, [r1, 0xD]\n" + "\tcmp r0, 0\n" + "\tbeq _0800D0EA\n" + "\tmovs r5, 0x1\n" + "\tldr r0, =gUnknown_03007890\n" + "\tldr r0, [r0]\n" + "\tldrb r0, [r0, 0x6]\n" + "\tcmp r0, 0\n" + "\tbeq _0800D0CE\n" + "\tldrb r0, [r1, 0x3]\n" + "\tldrb r1, [r1]\n" + "\tands r0, r1\n" + "\tcmp r0, r1\n" + "\tbeq _0800D0CE\n" + "\tmovs r5, 0\n" + "_0800D0CE:\n" + "\tcmp r5, 0\n" + "\tbeq _0800D0EA\n" + "\tldr r4, =gUnknown_03004140\n" + "\tldrb r0, [r4, 0xD]\n" + "\tbl sub_800D334\n" + "\tldrb r0, [r4, 0xD]\n" + "\tmovs r1, 0\n" + "\tstrh r0, [r4, 0x14]\n" + "\tstrb r1, [r4, 0xD]\n" + "\tmovs r0, 0x12\n" + "\tmovs r1, 0x1\n" + "\tbl sub_800D30C\n" + "_0800D0EA:\n" + "\tldr r0, =gUnknown_03004140\n" + "\tadds r1, r0, 0\n" + "\tadds r1, 0x24\n" + "\tldrb r1, [r1]\n" + "\tadds r3, r0, 0\n" + "\tcmp r1, 0\n" + "\tbne _0800D146_break\n" + "\tldrb r0, [r3, 0x4]\n" + "\tcmp r0, 0x8\n" + "\tbne _0800D146_break\n" + "\tldrb r0, [r3, 0x7]\n" + "\tcmp r0, 0\n" + "\tbne _0800D120\n" + "\tstrb r0, [r3, 0x5]\n" + "\tstrb r0, [r3, 0x4]\n" + "\tmovs r0, 0x14\n" + "\tmovs r1, 0\n" + "\tbl sub_800D30C\n" + "\tb _0800D146_break\n" + "\t.pool\n" + "_0800D120:\n" + "\tcmp r0, 0x2\n" + "\tbne _0800D12C\n" + "\tmovs r0, 0x3\n" + "\tstrb r0, [r3, 0x7]\n" + "\tmovs r0, 0x9\n" + "\tb _0800D132\n" + "_0800D12C:\n" + "\tmovs r0, 0x1\n" + "\tstrb r0, [r3, 0x7]\n" + "\tmovs r0, 0x5\n" + "_0800D132:\n" + "\tstrb r0, [r3, 0x4]\n" + "\tldrb r0, [r3]\n" + "\tcmp r0, 0\n" + "\tbeq _0800D146_break\n" + "\tmovs r0, 0\n" + "\tstrh r0, [r3, 0x1A]\n" + "\tmovs r0, 0x8\n" + "\tstrb r0, [r3, 0x7]\n" + "\tmovs r0, 0x5\n" + "\tstrb r0, [r3, 0x4]\n" + "_0800D146_break:\n" + "\tadd sp, 0x8\n" + "\tpop {r3-r5}\n" + "\tmov r8, r3\n" + "\tmov r9, r4\n" + "\tmov r10, r5\n" + "\tpop {r4-r7}\n" + "\tpop {r0}\n" + "\tbx r0"); +} +#endif