mirror of
https://github.com/Ninjdai1/pokeemerald.git
synced 2024-12-25 11:14:15 +01:00
more work on battle transition
This commit is contained in:
parent
ba176dfe07
commit
eb00e8ba4a
File diff suppressed because it is too large
Load Diff
@ -498,8 +498,8 @@ _080B5E68:
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bx r1
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bx r1
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thumb_func_end FieldEffectActiveListContains
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thumb_func_end FieldEffectActiveListContains
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thumb_func_start sub_80B5E6C
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thumb_func_start CreateTrainerSprite
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sub_80B5E6C: @ 80B5E6C
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CreateTrainerSprite: @ 80B5E6C
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push {r4-r7,lr}
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push {r4-r7,lr}
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mov r7, r9
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mov r7, r9
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mov r6, r8
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mov r6, r8
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@ -566,7 +566,7 @@ sub_80B5E6C: @ 80B5E6C
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pop {r1}
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pop {r1}
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bx r1
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bx r1
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.pool
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.pool
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thumb_func_end sub_80B5E6C
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thumb_func_end CreateTrainerSprite
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thumb_func_start sub_80B5F0C
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thumb_func_start sub_80B5F0C
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sub_80B5F0C: @ 80B5F0C
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sub_80B5F0C: @ 80B5F0C
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@ -3948,7 +3948,7 @@ AddBirchSpeechObjects: @ 803192C
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movs r1, 0x78
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movs r1, 0x78
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movs r2, 0x3C
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movs r2, 0x3C
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movs r3, 0
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movs r3, 0
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bl sub_80B5E6C
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bl CreateTrainerSprite
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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lsls r2, r0, 4
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lsls r2, r0, 4
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@ -3981,7 +3981,7 @@ AddBirchSpeechObjects: @ 803192C
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movs r1, 0x78
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movs r1, 0x78
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movs r2, 0x3C
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movs r2, 0x3C
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movs r3, 0
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movs r3, 0
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bl sub_80B5E6C
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bl CreateTrainerSprite
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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lsls r2, r0, 4
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lsls r2, r0, 4
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@ -24,8 +24,8 @@ _081DABD2:
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bx r1
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bx r1
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thumb_func_end sub_81DABBC
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thumb_func_end sub_81DABBC
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thumb_func_start Phase2Task_Transition_34
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thumb_func_start Phase2Task_34
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Phase2Task_Transition_34: @ 81DABDC
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Phase2Task_34: @ 81DABDC
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push {r4,r5,lr}
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push {r4,r5,lr}
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -50,7 +50,7 @@ _081DABEE:
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pop {r0}
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pop {r0}
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bx r0
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bx r0
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.pool
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.pool
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thumb_func_end Phase2Task_Transition_34
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thumb_func_end Phase2Task_34
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thumb_func_start sub_81DAC14
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thumb_func_start sub_81DAC14
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sub_81DAC14: @ 81DAC14
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sub_81DAC14: @ 81DAC14
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@ -119,7 +119,7 @@ sub_81DAC80: @ 81DAC80
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bne _081DACA4
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bne _081DACA4
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adds r0, r2, 0
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adds r0, r2, 0
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bl sub_81DAA20
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bl sub_81DAA20
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ldr r0, =Phase2Task_Transition_34
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ldr r0, =Phase2Task_34
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bl FindTaskIdByFunc
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bl FindTaskIdByFunc
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -131,8 +131,8 @@ _081DACA4:
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.pool
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.pool
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thumb_func_end sub_81DAC80
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thumb_func_end sub_81DAC80
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thumb_func_start Phase2Task_Transition_35
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thumb_func_start Phase2Task_35
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Phase2Task_Transition_35: @ 81DACB4
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Phase2Task_35: @ 81DACB4
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push {r4,r5,lr}
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push {r4,r5,lr}
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -157,7 +157,7 @@ _081DACC6:
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pop {r0}
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pop {r0}
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bx r0
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bx r0
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.pool
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.pool
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thumb_func_end Phase2Task_Transition_35
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thumb_func_end Phase2Task_35
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thumb_func_start sub_81DACEC
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thumb_func_start sub_81DACEC
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sub_81DACEC: @ 81DACEC
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sub_81DACEC: @ 81DACEC
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@ -226,7 +226,7 @@ sub_81DAD58: @ 81DAD58
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bne _081DAD7C
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bne _081DAD7C
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adds r0, r2, 0
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adds r0, r2, 0
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bl sub_81DAA20
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bl sub_81DAA20
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ldr r0, =Phase2Task_Transition_35
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ldr r0, =Phase2Task_35
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bl FindTaskIdByFunc
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bl FindTaskIdByFunc
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -238,8 +238,8 @@ _081DAD7C:
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.pool
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.pool
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thumb_func_end sub_81DAD58
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thumb_func_end sub_81DAD58
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thumb_func_start Phase2Task_Transition_36
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thumb_func_start Phase2Task_36
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Phase2Task_Transition_36: @ 81DAD8C
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Phase2Task_36: @ 81DAD8C
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push {r4,r5,lr}
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push {r4,r5,lr}
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -264,7 +264,7 @@ _081DAD9E:
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pop {r0}
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pop {r0}
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bx r0
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bx r0
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.pool
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.pool
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thumb_func_end Phase2Task_Transition_36
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thumb_func_end Phase2Task_36
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thumb_func_start sub_81DADC4
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thumb_func_start sub_81DADC4
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sub_81DADC4: @ 81DADC4
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sub_81DADC4: @ 81DADC4
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@ -342,7 +342,7 @@ sub_81DAE44: @ 81DAE44
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bne _081DAE68
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bne _081DAE68
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adds r0, r2, 0
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adds r0, r2, 0
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bl sub_81DAA20
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bl sub_81DAA20
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ldr r0, =Phase2Task_Transition_36
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ldr r0, =Phase2Task_36
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bl FindTaskIdByFunc
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bl FindTaskIdByFunc
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -354,8 +354,8 @@ _081DAE68:
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.pool
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.pool
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thumb_func_end sub_81DAE44
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thumb_func_end sub_81DAE44
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thumb_func_start Phase2Task_Transition_37
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thumb_func_start Phase2Task_37
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Phase2Task_Transition_37: @ 81DAE78
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Phase2Task_37: @ 81DAE78
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push {r4,r5,lr}
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push {r4,r5,lr}
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -380,7 +380,7 @@ _081DAE8A:
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pop {r0}
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pop {r0}
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bx r0
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bx r0
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.pool
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.pool
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thumb_func_end Phase2Task_Transition_37
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thumb_func_end Phase2Task_37
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thumb_func_start sub_81DAEB0
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thumb_func_start sub_81DAEB0
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sub_81DAEB0: @ 81DAEB0
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sub_81DAEB0: @ 81DAEB0
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@ -460,7 +460,7 @@ sub_81DAF34: @ 81DAF34
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bne _081DAF58
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bne _081DAF58
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adds r0, r2, 0
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adds r0, r2, 0
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bl sub_81DAA20
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bl sub_81DAA20
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ldr r0, =Phase2Task_Transition_37
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ldr r0, =Phase2Task_37
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bl FindTaskIdByFunc
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bl FindTaskIdByFunc
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -472,8 +472,8 @@ _081DAF58:
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.pool
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.pool
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thumb_func_end sub_81DAF34
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thumb_func_end sub_81DAF34
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thumb_func_start Phase2Task_Transition_38
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thumb_func_start Phase2Task_38
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Phase2Task_Transition_38: @ 81DAF68
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Phase2Task_38: @ 81DAF68
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push {r4,r5,lr}
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push {r4,r5,lr}
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -498,7 +498,7 @@ _081DAF7A:
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pop {r0}
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pop {r0}
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bx r0
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bx r0
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.pool
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.pool
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thumb_func_end Phase2Task_Transition_38
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thumb_func_end Phase2Task_38
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thumb_func_start sub_81DAFA0
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thumb_func_start sub_81DAFA0
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sub_81DAFA0: @ 81DAFA0
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sub_81DAFA0: @ 81DAFA0
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@ -585,7 +585,7 @@ sub_81DB02C: @ 81DB02C
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bne _081DB050
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bne _081DB050
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adds r0, r2, 0
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adds r0, r2, 0
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bl sub_81DAA20
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bl sub_81DAA20
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ldr r0, =Phase2Task_Transition_38
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ldr r0, =Phase2Task_38
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bl FindTaskIdByFunc
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bl FindTaskIdByFunc
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -597,8 +597,8 @@ _081DB050:
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.pool
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.pool
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thumb_func_end sub_81DB02C
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thumb_func_end sub_81DB02C
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thumb_func_start Phase2Task_Transition_39
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thumb_func_start Phase2Task_39
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Phase2Task_Transition_39: @ 81DB060
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Phase2Task_39: @ 81DB060
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push {r4,r5,lr}
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push {r4,r5,lr}
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -623,7 +623,7 @@ _081DB072:
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pop {r0}
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pop {r0}
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bx r0
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bx r0
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.pool
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.pool
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thumb_func_end Phase2Task_Transition_39
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thumb_func_end Phase2Task_39
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thumb_func_start sub_81DB098
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thumb_func_start sub_81DB098
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sub_81DB098: @ 81DB098
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sub_81DB098: @ 81DB098
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@ -710,7 +710,7 @@ sub_81DB124: @ 81DB124
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bne _081DB148
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bne _081DB148
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adds r0, r2, 0
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adds r0, r2, 0
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bl sub_81DAA20
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bl sub_81DAA20
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ldr r0, =Phase2Task_Transition_39
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ldr r0, =Phase2Task_39
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bl FindTaskIdByFunc
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bl FindTaskIdByFunc
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -722,8 +722,8 @@ _081DB148:
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.pool
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.pool
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thumb_func_end sub_81DB124
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thumb_func_end sub_81DB124
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thumb_func_start Phase2Task_Transition_40
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thumb_func_start Phase2Task_40
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Phase2Task_Transition_40: @ 81DB158
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Phase2Task_40: @ 81DB158
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push {r4,r5,lr}
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push {r4,r5,lr}
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -748,7 +748,7 @@ _081DB16A:
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pop {r0}
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pop {r0}
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bx r0
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bx r0
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.pool
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.pool
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thumb_func_end Phase2Task_Transition_40
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thumb_func_end Phase2Task_40
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thumb_func_start sub_81DB190
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thumb_func_start sub_81DB190
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sub_81DB190: @ 81DB190
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sub_81DB190: @ 81DB190
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@ -839,7 +839,7 @@ sub_81DB224: @ 81DB224
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bne _081DB248
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bne _081DB248
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adds r0, r2, 0
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adds r0, r2, 0
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bl sub_81DAA20
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bl sub_81DAA20
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ldr r0, =Phase2Task_Transition_40
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ldr r0, =Phase2Task_40
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bl FindTaskIdByFunc
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bl FindTaskIdByFunc
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -851,8 +851,8 @@ _081DB248:
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.pool
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.pool
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thumb_func_end sub_81DB224
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thumb_func_end sub_81DB224
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thumb_func_start Phase2Task_Transition_41
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thumb_func_start Phase2Task_41
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Phase2Task_Transition_41: @ 81DB258
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Phase2Task_41: @ 81DB258
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push {r4,r5,lr}
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push {r4,r5,lr}
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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@ -877,7 +877,7 @@ _081DB26A:
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pop {r0}
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pop {r0}
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bx r0
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bx r0
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.pool
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.pool
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thumb_func_end Phase2Task_Transition_41
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thumb_func_end Phase2Task_41
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thumb_func_start sub_81DB290
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thumb_func_start sub_81DB290
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sub_81DB290: @ 81DB290
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sub_81DB290: @ 81DB290
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@ -970,7 +970,7 @@ sub_81DB328: @ 81DB328
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bne _081DB34C
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bne _081DB34C
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adds r0, r2, 0
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adds r0, r2, 0
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bl sub_81DAA20
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bl sub_81DAA20
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ldr r0, =Phase2Task_Transition_41
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ldr r0, =Phase2Task_41
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bl FindTaskIdByFunc
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bl FindTaskIdByFunc
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lsls r0, 24
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lsls r0, 24
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lsrs r0, 24
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lsrs r0, 24
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||||||
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@ -4,175 +4,6 @@
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.section .rodata
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.section .rodata
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.align 2
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sPhase2_Transition_Blur_Funcs:: @ 85C8AA8
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.4byte sub_8146144
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.4byte sub_8146178
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.4byte sub_81461D8
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.align 2
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sPhase2_Transition_Swirl_Funcs:: @ 85C8AB4
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.4byte sub_814623C
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.4byte sub_81462A8
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|
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.align 2
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sPhase2_Transition_Shuffle_Funcs:: @ 85C8ABC
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.4byte sub_81463BC
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.4byte sub_8146420
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|
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.align 2
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gUnknown_085C8AC4:: @ 85C8AC4
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.4byte sub_814670C
|
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.4byte sub_81468E4
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.4byte sub_8146BF8
|
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.4byte sub_8146C8C
|
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.4byte sub_8146D20
|
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.4byte sub_8146D90
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.4byte sub_8146DF8
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|
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.align 2
|
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gUnknown_085C8AE0:: @ 85C8AE0
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.4byte sub_8146760
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.4byte sub_814692C
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.4byte sub_8146BF8
|
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.4byte sub_8146C8C
|
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.4byte sub_8146D20
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.4byte sub_8146D90
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.4byte sub_8146DF8
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|
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.align 2
|
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gUnknown_085C8AFC:: @ 85C8AFC
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.4byte sub_8146800
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.4byte sub_8146854
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.4byte sub_8146BF8
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.4byte sub_8146C8C
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.4byte sub_8146D20
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.4byte sub_8146DF8
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|
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.align 2
|
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gUnknown_085C8B14:: @ 85C8B14
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.4byte sub_81467B4
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.4byte sub_8146974
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.4byte sub_8146BF8
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.4byte sub_8146C8C
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.4byte sub_8146D20
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.4byte sub_8146DF8
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.align 2
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gUnknown_085C8B2C:: @ 85C8B2C
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.4byte sub_81467B4
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.4byte sub_81469CC
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.4byte sub_8146BF8
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.4byte sub_8146C8C
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.4byte sub_8146D20
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|
||||||
.4byte sub_8146DF8
|
|
||||||
|
|
||||||
.align 2
|
|
||||||
gUnknown_085C8B44:: @ 85C8B44
|
|
||||||
.4byte sub_81467B4
|
|
||||||
.4byte sub_8146A24
|
|
||||||
.4byte sub_8146BF8
|
|
||||||
.4byte sub_8146C8C
|
|
||||||
.4byte sub_8146D20
|
|
||||||
.4byte sub_8146DF8
|
|
||||||
|
|
||||||
.align 2
|
|
||||||
gUnknown_085C8B5C:: @ 85C8B5C
|
|
||||||
.4byte sub_8146DAC
|
|
||||||
.4byte sub_8146DD8
|
|
||||||
.4byte sub_8146A7C
|
|
||||||
.4byte sub_8146AC8
|
|
||||||
.4byte sub_8146B24
|
|
||||||
.4byte sub_8146D90
|
|
||||||
.4byte sub_8146B7C
|
|
||||||
.4byte sub_8146BA8
|
|
||||||
|
|
||||||
.align 2
|
|
||||||
sPhase2_Transition_PokeballsTrail_Funcs:: @ 85C8B7C
|
|
||||||
.4byte sub_8146FCC
|
|
||||||
.4byte sub_8147018
|
|
||||||
.4byte sub_81470A4
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
sUnknown_085C8B88:: @ 85C8B88
|
|
||||||
.2byte 0xfff0, 0x0100
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
sUnknown_085C8B8C:: @ 85C8B8C
|
|
||||||
.2byte 0x0000, 0x0020, 0x0040, 0x0012, 0x0030
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
sUnknown_085C8B96:: @ 85C8B96
|
|
||||||
.2byte 0x0008, 0xfff8, 0x0000
|
|
||||||
|
|
||||||
.align 2
|
|
||||||
sPhase2_Transition_Clockwise_BlackFade_Funcs:: @ 85C8B9C
|
|
||||||
.4byte sub_814723C
|
|
||||||
.4byte sub_81472A4
|
|
||||||
.4byte sub_8147334
|
|
||||||
.4byte sub_8147428
|
|
||||||
.4byte sub_81474B0
|
|
||||||
.4byte sub_81475B0
|
|
||||||
.4byte sub_8147648
|
|
||||||
|
|
||||||
.align 2
|
|
||||||
sPhase2_Transition_Ripple_Funcs:: @ 85C8BB8
|
|
||||||
.4byte sub_8147750
|
|
||||||
.4byte sub_81477A8
|
|
||||||
|
|
||||||
.align 2
|
|
||||||
sPhase2_Transition_Wave_Funcs:: @ 85C8BC0
|
|
||||||
.4byte sub_8147924
|
|
||||||
.4byte sub_814797C
|
|
||||||
.4byte sub_8147A18
|
|
||||||
|
|
||||||
.align 2
|
|
||||||
sPhase2_Mugshot_Transition_Funcs:: @ 85C8BCC
|
|
||||||
.4byte sub_8147BBC
|
|
||||||
.4byte sub_8147C24
|
|
||||||
.4byte sub_8147CE4
|
|
||||||
.4byte sub_8147DD0
|
|
||||||
.4byte sub_8147E4C
|
|
||||||
.4byte sub_8147E88
|
|
||||||
.4byte sub_8147F40
|
|
||||||
.4byte sub_8148008
|
|
||||||
.4byte sub_8148040
|
|
||||||
.4byte sub_814808C
|
|
||||||
|
|
||||||
sMugshotsTrainerPicIDsTable:: @ 85C8BF4
|
|
||||||
.byte 0x24, 0x25, 0x26, 0x27, 0x36, 0x00
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
sMugshotsOpponentRotationScales:: @ 85C8BFA
|
|
||||||
.2byte 0x0200, 0x0200, 0x0200, 0x0200, 0x01b0, 0x01b0, 0x01a0, 0x01a0, 0x0188, 0x0188
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
sMugshotsOpponentCoords:: @ 85C8C0E
|
|
||||||
.2byte 0x0000, 0x0000, 0x0000, 0x0000, 0xfffc, 0x0004, 0x0000, 0x0005, 0xfff8, 0x0007, 0x0000
|
|
||||||
|
|
||||||
.align 2
|
|
||||||
sUnknown_085C8C24:: @ 85C8C24
|
|
||||||
.4byte sub_81483A8
|
|
||||||
.4byte sub_81483AC
|
|
||||||
.4byte sub_81483F8
|
|
||||||
.4byte sub_814842C
|
|
||||||
.4byte sub_81483A8
|
|
||||||
.4byte sub_8148458
|
|
||||||
.4byte sub_81483A8
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
sUnknown_085C8C40:: @ 85C8C40
|
|
||||||
.2byte 0x000c, 0xfff4
|
|
||||||
|
|
||||||
.align 1
|
|
||||||
sUnknown_085C8C44:: @ 85C8C44
|
|
||||||
.2byte 0xffff, 0x0001
|
|
||||||
|
|
||||||
.align 2
|
|
||||||
gUnknown_085C8C48:: @ 85C8C48
|
|
||||||
.4byte sub_8148508
|
|
||||||
.4byte sub_8148590
|
|
||||||
.4byte sub_814865C
|
|
||||||
|
|
||||||
.align 2
|
.align 2
|
||||||
gUnknown_085C8C54:: @ 85C8C54
|
gUnknown_085C8C54:: @ 85C8C54
|
||||||
@ -286,20 +117,20 @@ gUnknown_085C8D38:: @ 85C8D38
|
|||||||
.4byte gUnknown_085C8D18
|
.4byte gUnknown_085C8D18
|
||||||
|
|
||||||
.align 2
|
.align 2
|
||||||
gUnknown_085C8D40:: @ 85C8D40
|
sPhase2_Groudon_Funcs:: @ 85C8D40
|
||||||
.4byte sub_8146DAC
|
.4byte Phase2_WeatherTrio_Func1
|
||||||
.4byte sub_8146DD8
|
.4byte Phase2_WaitPaletteFade
|
||||||
.4byte sub_8149178
|
.4byte sub_8149178
|
||||||
.4byte sub_81491C8
|
.4byte sub_81491C8
|
||||||
.4byte sub_8149224
|
.4byte sub_8149224
|
||||||
.4byte sub_8146D90
|
.4byte Phase2_FramesCountdown
|
||||||
.4byte sub_8146B7C
|
.4byte Phase2_WeatherDuo_Func6
|
||||||
.4byte sub_8146BA8
|
.4byte Phase2_WeatherDuo_Func7
|
||||||
|
|
||||||
.align 2
|
.align 2
|
||||||
gUnknown_085C8D60:: @ 85C8D60
|
sPhase2_Rayquaza_Funcs:: @ 85C8D60
|
||||||
.4byte sub_8146DAC
|
.4byte Phase2_WeatherTrio_Func1
|
||||||
.4byte sub_8146DD8
|
.4byte Phase2_WaitPaletteFade
|
||||||
.4byte sub_81492B4
|
.4byte sub_81492B4
|
||||||
.4byte sub_8149358
|
.4byte sub_8149358
|
||||||
.4byte sub_8149388
|
.4byte sub_8149388
|
||||||
@ -329,7 +160,7 @@ sUnknown_085C8DB0:: @ 85C8DB0
|
|||||||
.4byte sub_8149A40
|
.4byte sub_8149A40
|
||||||
|
|
||||||
.align 2
|
.align 2
|
||||||
sPhase2_Transition_Shards_Funcs:: @ 85C8DBC
|
sPhase2_Shards_Funcs:: @ 85C8DBC
|
||||||
.4byte sub_8149AA4
|
.4byte sub_8149AA4
|
||||||
.4byte sub_8149B08
|
.4byte sub_8149B08
|
||||||
.4byte sub_8149B84
|
.4byte sub_8149B84
|
||||||
@ -481,10 +312,10 @@ sMugshotsTilemap:: @ 85C94D0
|
|||||||
gUnknown_085C99D0:: @ 85C99D0
|
gUnknown_085C99D0:: @ 85C99D0
|
||||||
.4byte sub_814A324
|
.4byte sub_814A324
|
||||||
.4byte sub_814A374
|
.4byte sub_814A374
|
||||||
.4byte sub_8146BF8
|
.4byte Phase2_BigPokeball_Func3
|
||||||
.4byte sub_8146C8C
|
.4byte Phase2_BigPokeball_Func4
|
||||||
.4byte sub_8146D20
|
.4byte Phase2_BigPokeball_Func5
|
||||||
.4byte sub_8146DF8
|
.4byte Phase2_BigPokeball_Func6
|
||||||
|
|
||||||
.align 2
|
.align 2
|
||||||
gUnknown_085C99E8:: @ 85C99E8
|
gUnknown_085C99E8:: @ 85C99E8
|
||||||
|
@ -256,7 +256,7 @@ gFieldEffectScript_Unknown44:: @ 82DBC45
|
|||||||
|
|
||||||
gFieldEffectScript_Unknown45:: @ 82DBC4B
|
gFieldEffectScript_Unknown45:: @ 82DBC4B
|
||||||
field_eff_loadpal gFieldEffectObjectPaletteInfo10
|
field_eff_loadpal gFieldEffectObjectPaletteInfo10
|
||||||
field_eff_callnative sub_81470D0
|
field_eff_callnative FldEff_Pokeball
|
||||||
field_eff_end
|
field_eff_end
|
||||||
|
|
||||||
gFieldEffectScript_HeartIcon:: @ 82DBC56
|
gFieldEffectScript_HeartIcon:: @ 82DBC56
|
||||||
|
@ -7,6 +7,16 @@ void BattleTransition_StartOnField(u8 transitionID);
|
|||||||
void BattleTransition_Start(u8 transitionID);
|
void BattleTransition_Start(u8 transitionID);
|
||||||
bool8 IsBattleTransitionDone(void);
|
bool8 IsBattleTransitionDone(void);
|
||||||
|
|
||||||
|
enum // TRANSITION_MUGSHOT
|
||||||
|
{
|
||||||
|
MUGSHOT_SYDNEY,
|
||||||
|
MUGSHOT_PHOEBE,
|
||||||
|
MUGSHOT_GLACIA,
|
||||||
|
MUGSHOT_DRAKE,
|
||||||
|
MUGSHOT_CHAMPION,
|
||||||
|
MUGSHOTS_COUNT
|
||||||
|
};
|
||||||
|
|
||||||
// credits for the names go to Dyskinesia and Tetrable
|
// credits for the names go to Dyskinesia and Tetrable
|
||||||
// names are naturally subject to change
|
// names are naturally subject to change
|
||||||
|
|
||||||
|
@ -75,5 +75,6 @@ u32 FieldEffectStart(u8);
|
|||||||
bool8 FieldEffectActiveListContains(u8 id);
|
bool8 FieldEffectActiveListContains(u8 id);
|
||||||
void sub_80B69DC(void);
|
void sub_80B69DC(void);
|
||||||
void FieldEffectStop(struct Sprite *sprite, u8 id);
|
void FieldEffectStop(struct Sprite *sprite, u8 id);
|
||||||
|
u8 CreateTrainerSprite(u8 trainerSpriteID, s16 x, s16 y, u8 subpriority, u8 *buffer);
|
||||||
|
|
||||||
#endif //GUARD_FIELD_EFFECTS_H
|
#endif //GUARD_FIELD_EFFECTS_H
|
||||||
|
@ -137,8 +137,6 @@
|
|||||||
#define REG_OFFSET_DMA3CNT_H 0xde
|
#define REG_OFFSET_DMA3CNT_H 0xde
|
||||||
|
|
||||||
#define REG_OFFSET_TMCNT 0x100
|
#define REG_OFFSET_TMCNT 0x100
|
||||||
#define REG_OFFSET_TMCNT_L 0x100
|
|
||||||
#define REG_OFFSET_TMCNT_H 0x102
|
|
||||||
#define REG_OFFSET_TM0CNT 0x100
|
#define REG_OFFSET_TM0CNT 0x100
|
||||||
#define REG_OFFSET_TM0CNT_L 0x100
|
#define REG_OFFSET_TM0CNT_L 0x100
|
||||||
#define REG_OFFSET_TM0CNT_H 0x102
|
#define REG_OFFSET_TM0CNT_H 0x102
|
||||||
@ -300,8 +298,6 @@
|
|||||||
#define REG_ADDR_DMA3CNT_H (REG_BASE + REG_OFFSET_DMA3CNT_H)
|
#define REG_ADDR_DMA3CNT_H (REG_BASE + REG_OFFSET_DMA3CNT_H)
|
||||||
|
|
||||||
#define REG_ADDR_TMCNT (REG_BASE + REG_OFFSET_TMCNT)
|
#define REG_ADDR_TMCNT (REG_BASE + REG_OFFSET_TMCNT)
|
||||||
#define REG_ADDR_TMCNT_L (REG_BASE + REG_OFFSET_TMCNT_L)
|
|
||||||
#define REG_ADDR_TMCNT_H (REG_BASE + REG_OFFSET_TMCNT_H)
|
|
||||||
#define REG_ADDR_TM0CNT (REG_BASE + REG_OFFSET_TM0CNT)
|
#define REG_ADDR_TM0CNT (REG_BASE + REG_OFFSET_TM0CNT)
|
||||||
#define REG_ADDR_TM0CNT_L (REG_BASE + REG_OFFSET_TM0CNT_L)
|
#define REG_ADDR_TM0CNT_L (REG_BASE + REG_OFFSET_TM0CNT_L)
|
||||||
#define REG_ADDR_TM0CNT_H (REG_BASE + REG_OFFSET_TM0CNT_H)
|
#define REG_ADDR_TM0CNT_H (REG_BASE + REG_OFFSET_TM0CNT_H)
|
||||||
@ -462,8 +458,6 @@
|
|||||||
#define REG_DMA3CNT_H (*(vu16 *)REG_ADDR_DMA3CNT_H)
|
#define REG_DMA3CNT_H (*(vu16 *)REG_ADDR_DMA3CNT_H)
|
||||||
|
|
||||||
#define REG_TMCNT(n) (*(vu16 *)(REG_ADDR_TMCNT + ((n) * 4)))
|
#define REG_TMCNT(n) (*(vu16 *)(REG_ADDR_TMCNT + ((n) * 4)))
|
||||||
#define REG_TMCNT_L(n) (*(vu16 *)(REG_ADDR_TMCNT_L + ((n) * 4)))
|
|
||||||
#define REG_TMCNT_H(n) (*(vu16 *)(REG_ADDR_TMCNT_H + ((n) * 4)))
|
|
||||||
#define REG_TM0CNT (*(vu32 *)REG_ADDR_TM0CNT)
|
#define REG_TM0CNT (*(vu32 *)REG_ADDR_TM0CNT)
|
||||||
#define REG_TM0CNT_L (*(vu16 *)REG_ADDR_TM0CNT_L)
|
#define REG_TM0CNT_L (*(vu16 *)REG_ADDR_TM0CNT_L)
|
||||||
#define REG_TM0CNT_H (*(vu16 *)REG_ADDR_TM0CNT_H)
|
#define REG_TM0CNT_H (*(vu16 *)REG_ADDR_TM0CNT_H)
|
||||||
@ -501,12 +495,12 @@
|
|||||||
// I/O register fields
|
// I/O register fields
|
||||||
|
|
||||||
// DISPCNT
|
// DISPCNT
|
||||||
#define DISPCNT_MODE_0 0x0000
|
#define DISPCNT_MODE_0 0x0000 // BG0: text, BG1: text, BG2: text, BG3: text
|
||||||
#define DISPCNT_MODE_1 0x0001
|
#define DISPCNT_MODE_1 0x0001 // BG0: text, BG1: text, BG2: affine, BG3: off
|
||||||
#define DISPCNT_MODE_2 0x0002
|
#define DISPCNT_MODE_2 0x0002 // BG0: off, BG1: off, BG2: affine, BG3: affine
|
||||||
#define DISPCNT_MODE_3 0x0003
|
#define DISPCNT_MODE_3 0x0003 // Bitmap mode, 240x160, BGR555 color
|
||||||
#define DISPCNT_MODE_4 0x0004
|
#define DISPCNT_MODE_4 0x0004 // Bitmap mode, 240x160, 256 color palette
|
||||||
#define DISPCNT_MODE_5 0x0005
|
#define DISPCNT_MODE_5 0x0005 // Bitmap mode, 160x128, BGR555 color
|
||||||
#define DISPCNT_OBJ_1D_MAP 0x0040
|
#define DISPCNT_OBJ_1D_MAP 0x0040
|
||||||
#define DISPCNT_FORCED_BLANK 0x0080
|
#define DISPCNT_FORCED_BLANK 0x0080
|
||||||
#define DISPCNT_BG0_ON 0x0100
|
#define DISPCNT_BG0_ON 0x0100
|
||||||
@ -527,7 +521,46 @@
|
|||||||
#define DISPSTAT_HBLANK_INTR 0x0010 // H-Blank interrupt enabled
|
#define DISPSTAT_HBLANK_INTR 0x0010 // H-Blank interrupt enabled
|
||||||
#define DISPSTAT_VCOUNT_INTR 0x0020 // V-Count interrupt enabled
|
#define DISPSTAT_VCOUNT_INTR 0x0020 // V-Count interrupt enabled
|
||||||
|
|
||||||
|
// BGCNT
|
||||||
|
#define BGCNT_PRIORITY(n) (n) // Values 0 - 3. Lower priority BGs will be drawn on top of higher priority BGs.
|
||||||
|
#define BGCNT_CHARBASE(n) ((n) << 2) // Values 0 - 3. Base block for tile pixel data.
|
||||||
|
#define BGCNT_MOSAIC 0x0040
|
||||||
|
#define BGCNT_16COLOR 0x0000 // 4 bits per pixel
|
||||||
|
#define BGCNT_256COLOR 0x0080 // 8 bits per pixel
|
||||||
|
#define BGCNT_SCREENBASE(n) ((n) << 8) // Values 0 - 31. Base block for tile map.
|
||||||
|
#define BGCNT_WRAP 0x2000 // Only affects affine BGs. Text BGs wrap by default.
|
||||||
|
#define BGCNT_TXT256x256 0x0000 // Internal screen size size of text mode BG in pixels.
|
||||||
|
#define BGCNT_TXT512x256 0x4000
|
||||||
|
#define BGCNT_TXT256x512 0x8000
|
||||||
|
#define BGCNT_TXT512x512 0xC000
|
||||||
|
#define BGCNT_AFF128x128 0x0000 // Internal screen size size of affine mode BG in pixels.
|
||||||
|
#define BGCNT_AFF256x256 0x4000
|
||||||
|
#define BGCNT_AFF512x512 0x8000
|
||||||
|
#define BGCNT_AFF1024x1024 0xC000
|
||||||
|
|
||||||
// BLDCNT
|
// BLDCNT
|
||||||
|
// Bits 0-5 select layers for the 1st target
|
||||||
|
#define BLDCNT_TGT1_BG0 (1 << 0)
|
||||||
|
#define BLDCNT_TGT1_BG1 (1 << 1)
|
||||||
|
#define BLDCNT_TGT1_BG2 (1 << 2)
|
||||||
|
#define BLDCNT_TGT1_BG3 (1 << 3)
|
||||||
|
#define BLDCNT_TGT1_OBJ (1 << 4)
|
||||||
|
#define BLDCNT_TGT1_BD (1 << 5)
|
||||||
|
// Bits 6-7 select the special effect
|
||||||
|
#define BLDCNT_EFFECT_NONE (0 << 6) // no special effect
|
||||||
|
#define BLDCNT_EFFECT_BLEND (1 << 6) // 1st+2nd targets mixed (controlled by BLDALPHA)
|
||||||
|
#define BLDCNT_EFFECT_LIGHTEN (2 << 6) // 1st target becomes whiter (controlled by BLDY)
|
||||||
|
#define BLDCNT_EFFECT_DARKEN (3 << 6) // 1st target becomes blacker (controlled by BLDY)
|
||||||
|
// Bits 8-13 select layers for the 2nd target
|
||||||
|
#define BLDCNT_TGT2_BG0 (1 << 8)
|
||||||
|
#define BLDCNT_TGT2_BG1 (1 << 9)
|
||||||
|
#define BLDCNT_TGT2_BG2 (1 << 10)
|
||||||
|
#define BLDCNT_TGT2_BG3 (1 << 11)
|
||||||
|
#define BLDCNT_TGT2_OBJ (1 << 12)
|
||||||
|
#define BLDCNT_TGT2_BD (1 << 13)
|
||||||
|
|
||||||
|
// BLDALPHA
|
||||||
|
#define BLDALPHA_BLEND(target1, target2) (((target2) << 8) | (target1))
|
||||||
|
|
||||||
// SOUNDCNT_H
|
// SOUNDCNT_H
|
||||||
#define SOUND_CGB_MIX_QUARTER 0x0000
|
#define SOUND_CGB_MIX_QUARTER 0x0000
|
||||||
@ -627,8 +660,8 @@
|
|||||||
#define KEY_INTR_ENABLE 0x0400
|
#define KEY_INTR_ENABLE 0x0400
|
||||||
#define KEY_OR_INTR 0x0000
|
#define KEY_OR_INTR 0x0000
|
||||||
#define KEY_AND_INTR 0x8000
|
#define KEY_AND_INTR 0x8000
|
||||||
|
#define DPAD_ANY 0x00F0
|
||||||
#define DPAD_ANY ((DPAD_RIGHT | DPAD_LEFT | DPAD_UP | DPAD_DOWN))
|
#define JOY_EXCL_DPAD 0x030F
|
||||||
|
|
||||||
// interrupt flags
|
// interrupt flags
|
||||||
#define INTR_FLAG_VBLANK (1 << 0)
|
#define INTR_FLAG_VBLANK (1 << 0)
|
||||||
|
@ -1,13 +1,13 @@
|
|||||||
#ifndef GUARD_UNK_TRANSITION_H
|
#ifndef GUARD_UNK_TRANSITION_H
|
||||||
#define GUARD_UNK_TRANSITION_H
|
#define GUARD_UNK_TRANSITION_H
|
||||||
|
|
||||||
void Phase2Task_Transition_34(u8 taskId);
|
void Phase2Task_34(u8 taskId);
|
||||||
void Phase2Task_Transition_35(u8 taskId);
|
void Phase2Task_35(u8 taskId);
|
||||||
void Phase2Task_Transition_36(u8 taskId);
|
void Phase2Task_36(u8 taskId);
|
||||||
void Phase2Task_Transition_37(u8 taskId);
|
void Phase2Task_37(u8 taskId);
|
||||||
void Phase2Task_Transition_38(u8 taskId);
|
void Phase2Task_38(u8 taskId);
|
||||||
void Phase2Task_Transition_39(u8 taskId);
|
void Phase2Task_39(u8 taskId);
|
||||||
void Phase2Task_Transition_40(u8 taskId);
|
void Phase2Task_40(u8 taskId);
|
||||||
void Phase2Task_Transition_41(u8 taskId);
|
void Phase2Task_41(u8 taskId);
|
||||||
|
|
||||||
#endif // GUARD_UNK_TRANSITION_H
|
#endif // GUARD_UNK_TRANSITION_H
|
||||||
|
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Reference in New Issue
Block a user