mirror of
https://github.com/Ninjdai1/pokeemerald.git
synced 2024-12-27 12:14:20 +01:00
196 lines
4.3 KiB
C
196 lines
4.3 KiB
C
#include "global.h"
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#include "gpu_regs.h"
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#define GPU_REG_BUF_SIZE 0x60
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#define GPU_REG_BUF(offset) (*(u16 *)(&sGpuRegBuffer[offset]))
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#define GPU_REG(offset) (*(vu16 *)(REG_BASE + offset))
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#define EMPTY_SLOT 0xFF
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static u8 sGpuRegBuffer[GPU_REG_BUF_SIZE];
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static u8 sGpuRegWaitingList[GPU_REG_BUF_SIZE];
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static volatile bool8 sGpuRegBufferLocked;
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static volatile bool8 sShouldSyncRegIE;
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static vu16 sRegIE;
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static void CopyBufferedValueToGpuReg(u8 regOffset);
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static void SyncRegIE(void);
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static void UpdateRegDispstatIntrBits(u16 regIE);
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void InitGpuRegManager(void)
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{
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s32 i;
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for (i = 0; i < GPU_REG_BUF_SIZE; i++)
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{
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sGpuRegBuffer[i] = 0;
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sGpuRegWaitingList[i] = EMPTY_SLOT;
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}
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sGpuRegBufferLocked = FALSE;
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sShouldSyncRegIE = FALSE;
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sRegIE = 0;
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}
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static void CopyBufferedValueToGpuReg(u8 regOffset)
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{
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if (regOffset == REG_OFFSET_DISPSTAT)
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{
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REG_DISPSTAT &= ~(DISPSTAT_HBLANK_INTR | DISPSTAT_VBLANK_INTR);
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REG_DISPSTAT |= GPU_REG_BUF(REG_OFFSET_DISPSTAT);
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}
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else
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{
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GPU_REG(regOffset) = GPU_REG_BUF(regOffset);
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}
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}
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void CopyBufferedValuesToGpuRegs(void)
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{
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if (!sGpuRegBufferLocked)
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{
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s32 i;
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for (i = 0; i < GPU_REG_BUF_SIZE; i++)
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{
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u8 regOffset = sGpuRegWaitingList[i];
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if (regOffset == EMPTY_SLOT)
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return;
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CopyBufferedValueToGpuReg(regOffset);
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sGpuRegWaitingList[i] = EMPTY_SLOT;
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}
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}
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}
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void SetGpuReg(u8 regOffset, u16 value)
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{
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if (regOffset < GPU_REG_BUF_SIZE)
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{
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u16 vcount;
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GPU_REG_BUF(regOffset) = value;
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vcount = REG_VCOUNT & 0xFF;
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if ((vcount >= 161 && vcount <= 225) || (REG_DISPCNT & DISPCNT_FORCED_BLANK))
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{
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CopyBufferedValueToGpuReg(regOffset);
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}
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else
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{
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s32 i;
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sGpuRegBufferLocked = TRUE;
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for (i = 0; i < GPU_REG_BUF_SIZE && sGpuRegWaitingList[i] != EMPTY_SLOT; i++)
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{
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if (sGpuRegWaitingList[i] == regOffset)
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{
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sGpuRegBufferLocked = FALSE;
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return;
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}
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}
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sGpuRegWaitingList[i] = regOffset;
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sGpuRegBufferLocked = FALSE;
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}
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}
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}
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void SetGpuReg_ForcedBlank(u8 regOffset, u16 value)
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{
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if (regOffset < GPU_REG_BUF_SIZE)
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{
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GPU_REG_BUF(regOffset) = value;
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if (REG_DISPCNT & DISPCNT_FORCED_BLANK)
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{
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CopyBufferedValueToGpuReg(regOffset);
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}
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else
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{
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s32 i;
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sGpuRegBufferLocked = TRUE;
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for (i = 0; i < GPU_REG_BUF_SIZE && sGpuRegWaitingList[i] != EMPTY_SLOT; i++)
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{
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if (sGpuRegWaitingList[i] == regOffset)
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{
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sGpuRegBufferLocked = FALSE;
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return;
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}
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}
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sGpuRegWaitingList[i] = regOffset;
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sGpuRegBufferLocked = FALSE;
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}
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}
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}
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u16 GetGpuReg(u8 regOffset)
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{
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if (regOffset == REG_OFFSET_DISPSTAT)
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return REG_DISPSTAT;
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if (regOffset == REG_OFFSET_VCOUNT)
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return REG_VCOUNT;
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return GPU_REG_BUF(regOffset);
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}
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void SetGpuRegBits(u8 regOffset, u16 mask)
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{
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u16 regValue = GPU_REG_BUF(regOffset);
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SetGpuReg(regOffset, regValue | mask);
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}
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void ClearGpuRegBits(u8 regOffset, u16 mask)
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{
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u16 regValue = GPU_REG_BUF(regOffset);
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SetGpuReg(regOffset, regValue & ~mask);
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}
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static void SyncRegIE(void)
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{
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if (sShouldSyncRegIE)
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{
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u16 temp = REG_IME;
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REG_IME = 0;
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REG_IE = sRegIE;
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REG_IME = temp;
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sShouldSyncRegIE = FALSE;
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}
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}
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void EnableInterrupts(u16 mask)
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{
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sRegIE |= mask;
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sShouldSyncRegIE = TRUE;
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SyncRegIE();
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UpdateRegDispstatIntrBits(sRegIE);
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}
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void DisableInterrupts(u16 mask)
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{
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sRegIE &= ~mask;
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sShouldSyncRegIE = TRUE;
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SyncRegIE();
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UpdateRegDispstatIntrBits(sRegIE);
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}
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static void UpdateRegDispstatIntrBits(u16 regIE)
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{
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u16 oldValue = GetGpuReg(REG_OFFSET_DISPSTAT) & (DISPSTAT_HBLANK_INTR | DISPSTAT_VBLANK_INTR);
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u16 newValue = 0;
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if (regIE & INTR_FLAG_VBLANK)
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newValue |= DISPSTAT_VBLANK_INTR;
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if (regIE & INTR_FLAG_HBLANK)
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newValue |= DISPSTAT_HBLANK_INTR;
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if (oldValue != newValue)
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SetGpuReg(REG_OFFSET_DISPSTAT, newValue);
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}
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