pokeemerald/gflib/gpu_regs.c

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#include "global.h"
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#include "gpu_regs.h"
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#define GPU_REG_BUF_SIZE 0x60
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#define GPU_REG_BUF(offset) (*(u16 *)(&sGpuRegBuffer[offset]))
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#define GPU_REG(offset) (*(vu16 *)(REG_BASE + offset))
#define EMPTY_SLOT 0xFF
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static u8 sGpuRegBuffer[GPU_REG_BUF_SIZE];
static u8 sGpuRegWaitingList[GPU_REG_BUF_SIZE];
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static volatile bool8 sGpuRegBufferLocked;
static volatile bool8 sShouldSyncRegIE;
static vu16 sRegIE;
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static void CopyBufferedValueToGpuReg(u8 regOffset);
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static void SyncRegIE(void);
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static void UpdateRegDispstatIntrBits(u16 regIE);
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void InitGpuRegManager(void)
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{
s32 i;
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for (i = 0; i < GPU_REG_BUF_SIZE; i++)
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{
sGpuRegBuffer[i] = 0;
sGpuRegWaitingList[i] = EMPTY_SLOT;
}
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sGpuRegBufferLocked = FALSE;
sShouldSyncRegIE = FALSE;
sRegIE = 0;
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}
static void CopyBufferedValueToGpuReg(u8 regOffset)
{
if (regOffset == REG_OFFSET_DISPSTAT)
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{
REG_DISPSTAT &= ~(DISPSTAT_HBLANK_INTR | DISPSTAT_VBLANK_INTR);
REG_DISPSTAT |= GPU_REG_BUF(REG_OFFSET_DISPSTAT);
}
else
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{
GPU_REG(regOffset) = GPU_REG_BUF(regOffset);
}
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}
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void CopyBufferedValuesToGpuRegs(void)
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{
if (!sGpuRegBufferLocked)
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{
s32 i;
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for (i = 0; i < GPU_REG_BUF_SIZE; i++)
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{
u8 regOffset = sGpuRegWaitingList[i];
if (regOffset == EMPTY_SLOT)
return;
CopyBufferedValueToGpuReg(regOffset);
sGpuRegWaitingList[i] = EMPTY_SLOT;
}
}
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}
void SetGpuReg(u8 regOffset, u16 value)
{
if (regOffset < GPU_REG_BUF_SIZE)
{
u16 vcount;
GPU_REG_BUF(regOffset) = value;
vcount = REG_VCOUNT & 0xFF;
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if ((vcount >= 161 && vcount <= 225) || (REG_DISPCNT & DISPCNT_FORCED_BLANK))
{
CopyBufferedValueToGpuReg(regOffset);
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}
else
{
s32 i;
sGpuRegBufferLocked = TRUE;
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for (i = 0; i < GPU_REG_BUF_SIZE && sGpuRegWaitingList[i] != EMPTY_SLOT; i++)
{
if (sGpuRegWaitingList[i] == regOffset)
{
sGpuRegBufferLocked = FALSE;
return;
}
}
sGpuRegWaitingList[i] = regOffset;
sGpuRegBufferLocked = FALSE;
}
}
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}
void SetGpuReg_ForcedBlank(u8 regOffset, u16 value)
{
if (regOffset < GPU_REG_BUF_SIZE)
{
GPU_REG_BUF(regOffset) = value;
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if (REG_DISPCNT & DISPCNT_FORCED_BLANK)
{
CopyBufferedValueToGpuReg(regOffset);
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}
else
{
s32 i;
sGpuRegBufferLocked = TRUE;
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for (i = 0; i < GPU_REG_BUF_SIZE && sGpuRegWaitingList[i] != EMPTY_SLOT; i++)
{
if (sGpuRegWaitingList[i] == regOffset)
{
sGpuRegBufferLocked = FALSE;
return;
}
}
sGpuRegWaitingList[i] = regOffset;
sGpuRegBufferLocked = FALSE;
}
}
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}
u16 GetGpuReg(u8 regOffset)
{
if (regOffset == REG_OFFSET_DISPSTAT)
return REG_DISPSTAT;
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if (regOffset == REG_OFFSET_VCOUNT)
return REG_VCOUNT;
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return GPU_REG_BUF(regOffset);
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}
void SetGpuRegBits(u8 regOffset, u16 mask)
{
u16 regValue = GPU_REG_BUF(regOffset);
SetGpuReg(regOffset, regValue | mask);
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}
void ClearGpuRegBits(u8 regOffset, u16 mask)
{
u16 regValue = GPU_REG_BUF(regOffset);
SetGpuReg(regOffset, regValue & ~mask);
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}
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static void SyncRegIE(void)
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{
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if (sShouldSyncRegIE)
{
u16 temp = REG_IME;
REG_IME = 0;
REG_IE = sRegIE;
REG_IME = temp;
sShouldSyncRegIE = FALSE;
}
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}
void EnableInterrupts(u16 mask)
{
sRegIE |= mask;
sShouldSyncRegIE = TRUE;
SyncRegIE();
UpdateRegDispstatIntrBits(sRegIE);
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}
void DisableInterrupts(u16 mask)
{
sRegIE &= ~mask;
sShouldSyncRegIE = TRUE;
SyncRegIE();
UpdateRegDispstatIntrBits(sRegIE);
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}
static void UpdateRegDispstatIntrBits(u16 regIE)
{
u16 oldValue = GetGpuReg(REG_OFFSET_DISPSTAT) & (DISPSTAT_HBLANK_INTR | DISPSTAT_VBLANK_INTR);
u16 newValue = 0;
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if (regIE & INTR_FLAG_VBLANK)
newValue |= DISPSTAT_VBLANK_INTR;
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if (regIE & INTR_FLAG_HBLANK)
newValue |= DISPSTAT_HBLANK_INTR;
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if (oldValue != newValue)
SetGpuReg(REG_OFFSET_DISPSTAT, newValue);
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}